419 static void __iomem *syscon_vbase;  variable
520 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
537 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
559 	val = readw(syscon_vbase + U300_SYSCON_CCR);  in syscon_get_perf()
675 	val |= readw(syscon_vbase + U300_SYSCON_CCR) &  in syscon_clk_set_rate()
677 	writew(val, syscon_vbase + U300_SYSCON_CCR);  in syscon_clk_set_rate()
896 		res_reg = syscon_vbase + U300_SYSCON_RSR;  in of_u300_syscon_clk_init()
897 		en_reg = syscon_vbase + U300_SYSCON_CESR;  in of_u300_syscon_clk_init()
900 		res_reg = syscon_vbase + U300_SYSCON_RFR;  in of_u300_syscon_clk_init()
901 		en_reg = syscon_vbase + U300_SYSCON_CEFR;  in of_u300_syscon_clk_init()
904 		res_reg = syscon_vbase + U300_SYSCON_RRR;  in of_u300_syscon_clk_init()
905 		en_reg = syscon_vbase + U300_SYSCON_CERR;  in of_u300_syscon_clk_init()
960 		writew(0x0054U, syscon_vbase + U300_SYSCON_MMF0R);  in mclk_clk_prepare()
961 		val = readw(syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
966 		writew(val, syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
968 		val = readw(syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
973 		writew(val, syscon_vbase + U300_SYSCON_MMCR);  in mclk_clk_prepare()
1011 		u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) &  in mclk_clk_recalc_rate()
1102 	reg = readw(syscon_vbase + U300_SYSCON_MMF0R) &  in mclk_clk_set_rate()
1104 	writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R);  in mclk_clk_set_rate()
1183 	syscon_vbase = base;  in u300_clk_init()
1186 	val = readw(syscon_vbase + U300_SYSCON_CCR);  in u300_clk_init()
1188 	writew(val, syscon_vbase + U300_SYSCON_CCR);  in u300_clk_init()
1190 	while (!(readw(syscon_vbase + U300_SYSCON_CSR) &  in u300_clk_init()
1194 	val = readw(syscon_vbase + U300_SYSCON_PMCR);  in u300_clk_init()
1196 	writew(val, syscon_vbase + U300_SYSCON_PMCR);  in u300_clk_init()