Lines Matching +full:apb3 +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
139 /* Micro-controller output clock parent */
178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()
183 } while (bit_status && --timeout); in ready_gate_clk_enable()
201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()
206 } while (bit_status && --timeout); in ready_gate_clk_disable()
227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()
235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()
236 rgate->gate.lock = lock; in clk_register_ready_gate()
237 rgate->gate.reg = reg; in clk_register_ready_gate()
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
239 rgate->gate.hw.init = &init; in clk_register_ready_gate()
241 hw = &rgate->gate.hw; in clk_register_ready_gate()
302 return ERR_PTR(-ENOMEM); in _get_cmux()
304 mux->reg = reg; in _get_cmux()
305 mux->shift = shift; in _get_cmux()
306 mux->mask = (1 << width) - 1; in _get_cmux()
307 mux->flags = flags; in _get_cmux()
308 mux->lock = lock; in _get_cmux()
321 return ERR_PTR(-ENOMEM); in _get_cdiv()
323 div->reg = reg; in _get_cdiv()
324 div->shift = shift; in _get_cdiv()
325 div->width = width; in _get_cdiv()
326 div->flags = flags; in _get_cdiv()
327 div->lock = lock; in _get_cdiv()
339 return ERR_PTR(-ENOMEM); in _get_cgate()
341 gate->reg = reg; in _get_cgate()
342 gate->bit_idx = bit_idx; in _get_cgate()
343 gate->flags = flags; in _get_cgate()
344 gate->lock = lock; in _get_cgate()
374 if (gcfg->mux && cfg->mux) { in get_cfg_composite_div()
375 mux = _get_cmux(base + cfg->mux->offset, in get_cfg_composite_div()
376 cfg->mux->shift, in get_cfg_composite_div()
377 cfg->mux->width, in get_cfg_composite_div()
378 gcfg->mux->flags, lock); in get_cfg_composite_div()
381 mux_hw = &mux->hw; in get_cfg_composite_div()
382 mux_ops = gcfg->mux->ops ? in get_cfg_composite_div()
383 gcfg->mux->ops : &clk_mux_ops; in get_cfg_composite_div()
387 if (gcfg->div && cfg->div) { in get_cfg_composite_div()
388 div = _get_cdiv(base + cfg->div->offset, in get_cfg_composite_div()
389 cfg->div->shift, in get_cfg_composite_div()
390 cfg->div->width, in get_cfg_composite_div()
391 gcfg->div->flags, lock); in get_cfg_composite_div()
394 div_hw = &div->hw; in get_cfg_composite_div()
395 div_ops = gcfg->div->ops ? in get_cfg_composite_div()
396 gcfg->div->ops : &clk_divider_ops; in get_cfg_composite_div()
400 if (gcfg->gate && cfg->gate) { in get_cfg_composite_div()
401 gate = _get_cgate(base + cfg->gate->offset, in get_cfg_composite_div()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
403 gcfg->gate->flags, lock); in get_cfg_composite_div()
406 gate_hw = &gate->hw; in get_cfg_composite_div()
407 gate_ops = gcfg->gate->ops ? in get_cfg_composite_div()
408 gcfg->gate->ops : &clk_gate_ops; in get_cfg_composite_div()
412 composite->mux_hw = mux_hw; in get_cfg_composite_div()
413 composite->mux_ops = mux_ops; in get_cfg_composite_div()
415 composite->div_hw = div_hw; in get_cfg_composite_div()
416 composite->div_ops = div_ops; in get_cfg_composite_div()
418 composite->gate_hw = gate_hw; in get_cfg_composite_div()
419 composite->gate_ops = gate_ops; in get_cfg_composite_div()
436 u32 dppre_shift = clk_elem->dppre_shift; in timer_ker_recalc_rate()
472 return ERR_PTR(-ENOMEM); in clk_register_stm32_timer_ker()
480 element->hw.init = &init; in clk_register_stm32_timer_ker()
481 element->lock = lock; in clk_register_stm32_timer_ker()
482 element->dppre_shift = dppre_shift; in clk_register_stm32_timer_ker()
484 hw = &element->hw; in clk_register_stm32_timer_ker()
512 /* CORE AND BUS */ in register_core_and_bus_clocks()
526 /* * APB3 peripheral */ in register_core_and_bus_clocks()
614 OSC_CLKF("csi_ck", "clk-csi", RCC_CR, 7, 8, CLK_IGNORE_UNUSED),
615 OSC_CLKF("csi_ker", "clk-csi", RCC_CR, 9, 8, CLK_IGNORE_UNUSED),
616 OSC_CLKF("rc48_ck", "clk-rc48", RCC_CR, 12, 13, CLK_IGNORE_UNUSED),
617 OSC_CLKF("lsi_ck", "clk-lsi", RCC_CSR, 0, 1, CLK_IGNORE_UNUSED),
699 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_is_enabled()
709 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_enable()
719 struct clk_hw *_hw = &clk_elem->rgate.gate.hw; in pll_disable()
729 struct stm32_fractional_divider *fd = &clk_elem->div; in pll_frac_is_enabled()
731 return (readl(fd->freg_status) >> fd->freg_bit) & 0x01; in pll_frac_is_enabled()
737 struct stm32_fractional_divider *fd = &clk_elem->div; in pll_read_frac()
739 return (readl(fd->freg_value) >> fd->fshift) & in pll_read_frac()
740 GENMASK(fd->fwidth - 1, 0); in pll_read_frac()
747 struct stm32_fractional_divider *fd = &clk_elem->div; in pll_fd_recalc_rate()
752 val = readl(fd->mreg); in pll_fd_recalc_rate()
753 mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift; in pll_fd_recalc_rate()
754 m = (val & mask) >> fd->mshift; in pll_fd_recalc_rate()
756 val = readl(fd->nreg); in pll_fd_recalc_rate()
757 mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift; in pll_fd_recalc_rate()
758 n = ((val & mask) >> fd->nshift) + 1; in pll_fd_recalc_rate()
798 return ERR_PTR(-ENOMEM); in clk_register_stm32_pll()
805 pll->hw.init = &init; in clk_register_stm32_pll()
807 hw = &pll->hw; in clk_register_stm32_pll()
808 rgate = &pll->rgate; in clk_register_stm32_pll()
810 rgate->bit_rdy = cfg->bit_idx + 1; in clk_register_stm32_pll()
811 rgate->gate.lock = lock; in clk_register_stm32_pll()
812 rgate->gate.reg = base + RCC_CR; in clk_register_stm32_pll()
813 rgate->gate.bit_idx = cfg->bit_idx; in clk_register_stm32_pll()
815 div = &pll->div; in clk_register_stm32_pll()
816 div->flags = 0; in clk_register_stm32_pll()
817 div->mreg = base + RCC_PLLCKSELR; in clk_register_stm32_pll()
818 div->mshift = cfg->divm; in clk_register_stm32_pll()
819 div->mwidth = 6; in clk_register_stm32_pll()
820 div->nreg = base + cfg->offset_divr; in clk_register_stm32_pll()
821 div->nshift = 0; in clk_register_stm32_pll()
822 div->nwidth = 9; in clk_register_stm32_pll()
824 div->freg_status = base + RCC_PLLCFGR; in clk_register_stm32_pll()
825 div->freg_bit = cfg->bit_frac_en; in clk_register_stm32_pll()
826 div->freg_value = base + cfg->offset_frac; in clk_register_stm32_pll()
827 div->fshift = 3; in clk_register_stm32_pll()
828 div->fwidth = 13; in clk_register_stm32_pll()
830 div->lock = lock; in clk_register_stm32_pll()
1172 /* Micro-controller output clock */
1209 clk_data->num = STM32H7_MAX_CLKS; in stm32h7_rcc_init()
1211 hws = clk_data->hws; in stm32h7_rcc_init()
1214 hws[n] = ERR_PTR(-ENOENT); in stm32h7_rcc_init()
1242 clk_hw_register_fixed_rate(NULL, "clk-hsi", NULL, 0, 64000000); in stm32h7_rcc_init()
1243 clk_hw_register_fixed_rate(NULL, "clk-csi", NULL, 0, 4000000); in stm32h7_rcc_init()
1244 clk_hw_register_fixed_rate(NULL, "clk-lsi", NULL, 0, 32000); in stm32h7_rcc_init()
1245 clk_hw_register_fixed_rate(NULL, "clk-rc48", NULL, 0, 48000); in stm32h7_rcc_init()
1251 hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0, in stm32h7_rcc_init()
1369 /* Micro-controller clocks */ in stm32h7_rcc_init()
1396 CLK_OF_DECLARE_DRIVER(stm32h7_rcc, "st,stm32h743-rcc", stm32h7_rcc_init);