18  * rate - rate is fixed.  clk->rate = parent->rate / div * mult
28 	rate = (unsigned long long int)parent_rate * fix->mult;  in clk_factor_recalc_rate()
41 		best_parent = (rate / fix->mult) * fix->div;  in clk_factor_round_rate()
45 	return (*prate / fix->div) * fix->mult;  in clk_factor_round_rate()
70 		unsigned long flags, unsigned int mult, unsigned int div)  in __clk_hw_register_fixed_factor()  argument
83 	fix->mult = mult;  in __clk_hw_register_fixed_factor()
111 		unsigned int mult, unsigned int div)  in clk_hw_register_fixed_factor()  argument
114 					      flags, mult, div);  in clk_hw_register_fixed_factor()
120 		unsigned int mult, unsigned int div)  in clk_register_fixed_factor()  argument
124 	hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,  in clk_register_fixed_factor()
167 	u32 div, mult;  in _of_fixed_factor_clk_setup()  local
176 	if (of_property_read_u32(node, "clock-mult", &mult)) {  in _of_fixed_factor_clk_setup()
177 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",  in _of_fixed_factor_clk_setup()
188 					    flags, mult, div);  in _of_fixed_factor_clk_setup()