7  * Adjustable divider clock implementation
19  * DOC: basic adjustable divider clock that cannot gate
28 static inline u32 clk_div_readl(struct clk_divider *divider)  in clk_div_readl()  argument
30 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_readl()
31 		return ioread32be(divider->reg);  in clk_div_readl()
33 	return readl(divider->reg);  in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val)  in clk_div_writel()  argument
38 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_writel()
39 		iowrite32be(val, divider->reg);  in clk_div_writel()
41 		writel(val, divider->reg);  in clk_div_writel()
151 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_recalc_rate()  local
154 	val = clk_div_readl(divider) >> divider->shift;  in clk_divider_recalc_rate()
155 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
157 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
158 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
312 	 * The maximum divider we can use without overflowing  in clk_divider_bestdiv()
323 			 * parent rate, so return the divider immediately.  in clk_divider_bestdiv()
383 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_round_rate()  local
386 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
389 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_round_rate()
390 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
392 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
393 					     divider->width, divider->flags,  in clk_divider_round_rate()
397 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
398 				  divider->width, divider->flags);  in clk_divider_round_rate()
421 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_set_rate()  local
426 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
427 				divider->width, divider->flags);  in clk_divider_set_rate()
431 	if (divider->lock)  in clk_divider_set_rate()
432 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
434 		__acquire(divider->lock);  in clk_divider_set_rate()
436 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
437 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
439 		val = clk_div_readl(divider);  in clk_divider_set_rate()
440 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
442 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
443 	clk_div_writel(divider, val);  in clk_divider_set_rate()
445 	if (divider->lock)  in clk_divider_set_rate()
446 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
448 		__release(divider->lock);  in clk_divider_set_rate()
480 			pr_warn("divider value exceeds LOWORD field\n");  in __clk_hw_register_divider()
485 	/* allocate the divider */  in __clk_hw_register_divider()
521  * clk_register_divider_table - register a table based divider clock with
527  * @reg: register address to adjust divider
530  * @clk_divider_flags: divider-specific flags for this clock
531  * @table: array of divider/value pairs ending with a div set to 0
568  * clk_hw_unregister_divider - unregister a clk divider