Lines Matching +full:pre +full:- +full:determined

24 #include <linux/clk-provider.h>
32 #define BAD_CLK_NAME		((const char *)-1)
41 #define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
42 #define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
43 #define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
44 #define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
48 #define ccu_policy_exists(ccu_policy)	((ccu_policy)->enable.offset != 0)
52 #define policy_exists(policy)		((policy)->offset != 0)
63 #define hyst_exists(hyst)		((hyst)->offset != 0)
68 						(div)->u.s.frac_width > 0)
70 #define selector_exists(sel)		((sel)->width != 0)
73 #define policy_lvm_en_exists(enable)	((enable)->offset != 0)
74 #define policy_ctl_exists(control)	((control)->offset != 0)
106  * Gating control and status is managed by a 32-bit gate register.
109  * - (no gate)
111  * - hardware-only gating (auto-gating)
115  *     of auto-gated clocks can be read from the gate status bit.
116  * - software-only gating
117  *     Auto-gating is not available for this type of clock.
124  * - selectable hardware or software gating
127  *     determined by the hw_sw_sel bit of the gate register.
139  *   HW         means this gate can be auto-gated
143  *   ENABLED    means this software-managed gate is *supposed* to be enabled
146 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
181 /* A hardware-or-enabled gate (enabled if not under hardware control) */
192 /* A software-only gate */
202 /* A hardware-only gate */
229  * variable.  If there are two dividers, they are the "pre-divider"
231  * there is no pre-divider.
233  * A fixed divider is any non-zero (positive) value, and it
236  * The value of a variable divider is maintained in a sub-field of a
237  * 32-bit divider register.  The position of the field in the
243  * bits comprise the low-order portion of the divider field, and can
246  * fractional bits.  Variable dividers with non-zero fraction width
248  * added 1 does *not* affect the low-order bit in this case, it
255  * been left-shifted by the fractional width of a divider.  Dividing
276 		u32 fixed;	/* non-zero fixed divider value */
284  *   FIXED means it is a fixed-rate divider
287 #define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
291 /* A fixed (non-zero) divider */
323  * sub-field of a 32-bit selector register.  The range of
367  * case, the "pre-trigger" will be used when changing a clock's
368  * selector and/or its pre-divider.