Lines Matching +full:clock +full:- +full:name
18 #include "clk-kona.h"
21 #define selector_clear_exists(sel) ((sel)->width = 0)
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
34 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
40 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
53 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
57 if (bcm_clk->type != bcm_clk_peri) in clk_requires_trigger()
60 sel = &peri->sel; in clk_requires_trigger()
61 if (sel->parent_count && selector_exists(sel)) in clk_requires_trigger()
64 div = &peri->div; in clk_requires_trigger()
72 div = &peri->pre_div; in clk_requires_trigger()
86 const char *name; in peri_clk_data_offsets_valid() local
90 BUG_ON(bcm_clk->type != bcm_clk_peri); in peri_clk_data_offsets_valid()
91 peri = bcm_clk->u.peri; in peri_clk_data_offsets_valid()
92 name = bcm_clk->init_data.name; in peri_clk_data_offsets_valid()
93 range = bcm_clk->ccu->range; in peri_clk_data_offsets_valid()
95 limit = range - sizeof(u32); in peri_clk_data_offsets_valid()
98 policy = &peri->policy; in peri_clk_data_offsets_valid()
100 if (policy->offset > limit) { in peri_clk_data_offsets_valid()
102 __func__, name, policy->offset, limit); in peri_clk_data_offsets_valid()
107 gate = &peri->gate; in peri_clk_data_offsets_valid()
108 hyst = &peri->hyst; in peri_clk_data_offsets_valid()
110 if (gate->offset > limit) { in peri_clk_data_offsets_valid()
112 __func__, name, gate->offset, limit); in peri_clk_data_offsets_valid()
117 if (hyst->offset > limit) { in peri_clk_data_offsets_valid()
120 name, hyst->offset, limit); in peri_clk_data_offsets_valid()
125 pr_err("%s: hysteresis but no gate for %s\n", __func__, name); in peri_clk_data_offsets_valid()
129 div = &peri->div; in peri_clk_data_offsets_valid()
131 if (div->u.s.offset > limit) { in peri_clk_data_offsets_valid()
133 __func__, name, div->u.s.offset, limit); in peri_clk_data_offsets_valid()
138 div = &peri->pre_div; in peri_clk_data_offsets_valid()
140 if (div->u.s.offset > limit) { in peri_clk_data_offsets_valid()
141 pr_err("%s: bad pre-divider offset for %s " in peri_clk_data_offsets_valid()
143 __func__, name, div->u.s.offset, limit); in peri_clk_data_offsets_valid()
148 sel = &peri->sel; in peri_clk_data_offsets_valid()
150 if (sel->offset > limit) { in peri_clk_data_offsets_valid()
152 __func__, name, sel->offset, limit); in peri_clk_data_offsets_valid()
157 trig = &peri->trig; in peri_clk_data_offsets_valid()
159 if (trig->offset > limit) { in peri_clk_data_offsets_valid()
161 __func__, name, trig->offset, limit); in peri_clk_data_offsets_valid()
166 trig = &peri->pre_trig; in peri_clk_data_offsets_valid()
168 if (trig->offset > limit) { in peri_clk_data_offsets_valid()
169 pr_err("%s: bad pre-trigger offset for %s (%u > %u)\n", in peri_clk_data_offsets_valid()
170 __func__, name, trig->offset, limit); in peri_clk_data_offsets_valid()
178 /* A bit position must be less than the number of bits in a 32-bit register. */
182 u32 limit = BITS_PER_BYTE * sizeof(u32) - 1; in bit_posn_valid()
193 * A bitfield must be at least 1 bit wide. Both the low-order and
194 * high-order bits must lie within a 32-bit register. We require
197 * is not well-defined by the C standard.
220 struct bcm_lvm_en *enable = &ccu_policy->enable; in ccu_policy_valid()
223 if (!bit_posn_valid(enable->bit, "policy enable", ccu_name)) in ccu_policy_valid()
226 control = &ccu_policy->control; in ccu_policy_valid()
227 if (!bit_posn_valid(control->go_bit, "policy control GO", ccu_name)) in ccu_policy_valid()
230 if (!bit_posn_valid(control->atl_bit, "policy control ATL", ccu_name)) in ccu_policy_valid()
233 if (!bit_posn_valid(control->ac_bit, "policy control AC", ccu_name)) in ccu_policy_valid()
241 if (!bit_posn_valid(policy->bit, "policy", clock_name)) in policy_valid()
248 * All gates, if defined, have a status bit, and for hardware-only
256 if (!bit_posn_valid(gate->status_bit, "gate status", clock_name)) in gate_valid()
260 if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name)) in gate_valid()
264 if (!bit_posn_valid(gate->hw_sw_sel_bit, in gate_valid()
278 if (!bit_posn_valid(hyst->en_bit, "hysteresis enable", clock_name)) in hyst_valid()
281 if (!bit_posn_valid(hyst->val_bit, "hysteresis value", clock_name)) in hyst_valid()
294 if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name)) in sel_valid()
297 if (sel->parent_count) { in sel_valid()
304 * clock only needs to have a selector defined if it in sel_valid()
309 max_sel = sel->parent_sel[sel->parent_count - 1]; in sel_valid()
310 limit = (1 << sel->width) - 1; in sel_valid()
315 sel->width); in sel_valid()
322 kfree(sel->parent_sel); in sel_valid()
323 sel->parent_sel = NULL; in sel_valid()
330 * A fixed divider just needs to be non-zero. A variable divider
340 if (div->u.fixed == 0) { in div_valid()
347 if (!bitfield_valid(div->u.s.shift, div->u.s.width, in div_valid()
352 if (div->u.s.frac_width > div->u.s.width) { in div_valid()
355 div->u.s.frac_width, div->u.s.width); in div_valid()
363 * If a clock has two dividers, the combined number of fractional
364 * bits must be representable in a 32-bit unsigned value. This
370 struct peri_clk_data *peri = bcm_clk->u.peri; in kona_dividers_valid()
375 BUG_ON(bcm_clk->type != bcm_clk_peri); in kona_dividers_valid()
377 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div)) in kona_dividers_valid()
380 div = &peri->div; in kona_dividers_valid()
381 pre_div = &peri->pre_div; in kona_dividers_valid()
387 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; in kona_dividers_valid()
395 return bit_posn_valid(trig->bit, field_name, clock_name); in trig_valid()
398 /* Determine whether the set of peripheral clock registers are valid. */
410 const char *name; in peri_clk_data_valid() local
412 BUG_ON(bcm_clk->type != bcm_clk_peri); in peri_clk_data_valid()
422 peri = bcm_clk->u.peri; in peri_clk_data_valid()
423 name = bcm_clk->init_data.name; in peri_clk_data_valid()
425 policy = &peri->policy; in peri_clk_data_valid()
426 if (policy_exists(policy) && !policy_valid(policy, name)) in peri_clk_data_valid()
429 gate = &peri->gate; in peri_clk_data_valid()
430 if (gate_exists(gate) && !gate_valid(gate, "gate", name)) in peri_clk_data_valid()
433 hyst = &peri->hyst; in peri_clk_data_valid()
434 if (hyst_exists(hyst) && !hyst_valid(hyst, name)) in peri_clk_data_valid()
437 sel = &peri->sel; in peri_clk_data_valid()
439 if (!sel_valid(sel, "selector", name)) in peri_clk_data_valid()
442 } else if (sel->parent_count > 1) { in peri_clk_data_valid()
444 __func__, name); in peri_clk_data_valid()
449 div = &peri->div; in peri_clk_data_valid()
450 pre_div = &peri->pre_div; in peri_clk_data_valid()
452 if (!div_valid(div, "divider", name)) in peri_clk_data_valid()
456 if (!div_valid(pre_div, "pre-divider", name)) in peri_clk_data_valid()
459 pr_err("%s: pre-divider but no divider for %s\n", __func__, in peri_clk_data_valid()
460 name); in peri_clk_data_valid()
464 trig = &peri->trig; in peri_clk_data_valid()
466 if (!trig_valid(trig, "trigger", name)) in peri_clk_data_valid()
469 if (trigger_exists(&peri->pre_trig)) { in peri_clk_data_valid()
470 if (!trig_valid(trig, "pre-trigger", name)) { in peri_clk_data_valid()
476 __func__, name); in peri_clk_data_valid()
479 } else if (trigger_exists(&peri->pre_trig)) { in peri_clk_data_valid()
480 pr_err("%s: pre-trigger but no trigger for %s\n", __func__, in peri_clk_data_valid()
481 name); in peri_clk_data_valid()
485 name); in peri_clk_data_valid()
494 switch (bcm_clk->type) { in kona_clk_valid()
500 pr_err("%s: unrecognized clock type (%d)\n", __func__, in kona_clk_valid()
501 (int)bcm_clk->type); in kona_clk_valid()
508 * Scan an array of parent clock names to determine whether there
510 * placeholders for non-supported clocks. Keep track of the
511 * position of each clock name in the original array.
514 * non-null entries in the original array, and returns a pointer to
516 * clock with the common clock code. On successful return,
521 * for each (defined) parent clock. This is the value that
522 * represents this parent clock in the clock's source selector
523 * register. The position of the clock in the original parent array
527 * The array of selector values is returned. If the clock has no
530 * Returns a null pointer if the clock names array supplied was
533 * Returns a pointer-coded error if an error occurs.
540 const char **clock; in parent_process() local
553 * Count the number of names in the null-terminated array, in parent_process()
554 * and find out how many of those are actually clock names. in parent_process()
556 for (clock = clocks; *clock; clock++) in parent_process()
557 if (*clock == BAD_CLK_NAME) in parent_process()
559 orig_count = (u32)(clock - clocks); in parent_process()
560 parent_count = orig_count - bad_count; in parent_process()
562 /* If all clocks are unsupported, we treat it as no clock */ in parent_process()
566 /* Avoid exceeding our parent clock limit */ in parent_process()
570 return ERR_PTR(-EINVAL); in parent_process()
574 * There is one parent name for each defined parent clock. in parent_process()
576 * for each defined clock. If there's only one clock, the in parent_process()
583 return ERR_PTR(-ENOMEM); in parent_process()
591 return ERR_PTR(-ENOMEM); in parent_process()
617 * If a peripheral clock has multiple parents, the value in clk_sel_setup()
619 * by the parent clock's position in the "clocks" list. Some in clk_sel_setup()
625 * clocks when registering a clock though, so we use an in clk_sel_setup()
627 * indexes the common clock code uses and the selector in clk_sel_setup()
635 __func__, init_data->name, ret); in clk_sel_setup()
640 init_data->parent_names = parent_names; in clk_sel_setup()
641 init_data->num_parents = parent_count; in clk_sel_setup()
643 sel->parent_count = parent_count; in clk_sel_setup()
644 sel->parent_sel = parent_sel; in clk_sel_setup()
652 kfree(sel->parent_sel); in clk_sel_teardown()
653 sel->parent_sel = NULL; in clk_sel_teardown()
654 sel->parent_count = 0; in clk_sel_teardown()
656 init_data->num_parents = 0; in clk_sel_teardown()
657 kfree(init_data->parent_names); in clk_sel_teardown()
658 init_data->parent_names = NULL; in clk_sel_teardown()
664 clk_sel_teardown(&data->sel, init_data); in peri_clk_teardown()
669 * parent_sel[] arrays in the peripheral clock's "data" structure
670 * that can be assigned if the clock has one or more parent clocks
676 init_data->flags = CLK_IGNORE_UNUSED; in peri_clk_setup()
678 return clk_sel_setup(data->clocks, &data->sel, init_data); in peri_clk_setup()
683 switch (bcm_clk->type) { in bcm_clk_teardown()
685 peri_clk_teardown(bcm_clk->u.data, &bcm_clk->init_data); in bcm_clk_teardown()
690 bcm_clk->u.data = NULL; in bcm_clk_teardown()
691 bcm_clk->type = bcm_clk_none; in bcm_clk_teardown()
710 struct clk_init_data *init_data = &bcm_clk->init_data; in kona_clk_setup()
712 switch (bcm_clk->type) { in kona_clk_setup()
714 ret = peri_clk_setup(bcm_clk->u.data, init_data); in kona_clk_setup()
719 pr_err("%s: clock type %d invalid for %s\n", __func__, in kona_clk_setup()
720 (int)bcm_clk->type, init_data->name); in kona_clk_setup()
721 return -EINVAL; in kona_clk_setup()
726 pr_err("%s: clock data invalid for %s\n", __func__, in kona_clk_setup()
727 init_data->name); in kona_clk_setup()
728 ret = -EINVAL; in kona_clk_setup()
732 bcm_clk->hw.init = init_data; in kona_clk_setup()
733 ret = clk_hw_register(NULL, &bcm_clk->hw); in kona_clk_setup()
735 pr_err("%s: error registering clock %s (%d)\n", __func__, in kona_clk_setup()
736 init_data->name, ret); in kona_clk_setup()
751 for (i = 0; i < ccu->clk_num; i++) in ccu_clks_teardown()
752 kona_clk_teardown(&ccu->kona_clks[i].hw); in ccu_clks_teardown()
757 if (!ccu->base) in kona_ccu_teardown()
760 of_clk_del_provider(ccu->node); /* safe if never added */ in kona_ccu_teardown()
762 of_node_put(ccu->node); in kona_ccu_teardown()
763 ccu->node = NULL; in kona_ccu_teardown()
764 iounmap(ccu->base); in kona_ccu_teardown()
765 ccu->base = NULL; in kona_ccu_teardown()
775 ccu_policy = &ccu->policy; in ccu_data_valid()
777 if (!ccu_policy_valid(ccu_policy, ccu->name)) in ccu_data_valid()
787 unsigned int idx = clkspec->args[0]; in of_clk_kona_onecell_get()
789 if (idx >= ccu->clk_num) { in of_clk_kona_onecell_get()
791 return ERR_PTR(-EINVAL); in of_clk_kona_onecell_get()
794 return &ccu->kona_clks[idx].hw; in of_clk_kona_onecell_get()
823 ccu->range = (u32)range; in kona_dt_ccu_setup()
830 ccu->base = ioremap(res.start, ccu->range); in kona_dt_ccu_setup()
831 if (!ccu->base) { in kona_dt_ccu_setup()
836 ccu->node = of_node_get(node); in kona_dt_ccu_setup()
839 * Set up each defined kona clock and save the result in in kona_dt_ccu_setup()
840 * the clock framework clock array (in ccu->data). Then in kona_dt_ccu_setup()
843 for (i = 0; i < ccu->clk_num; i++) { in kona_dt_ccu_setup()
844 if (!ccu->kona_clks[i].ccu) in kona_dt_ccu_setup()
846 kona_clk_setup(&ccu->kona_clks[i]); in kona_dt_ccu_setup()