Lines Matching +full:8 +full:- +full:channel
16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
73 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
76 .mdiv = REG_VAL(0x20, 0, 8),
79 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
82 .mdiv = REG_VAL(0x20, 10, 8),
85 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
87 .enable = ENABLE_VAL(0x4, 8, 2, 14),
88 .mdiv = REG_VAL(0x20, 20, 8),
91 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
94 .mdiv = REG_VAL(0x24, 0, 8),
97 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
100 .mdiv = REG_VAL(0x24, 10, 8),
103 .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
106 .mdiv = REG_VAL(0x24, 20, 8),
115 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
131 .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
134 .mdiv = REG_VAL(0x8, 0, 8),
137 .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
139 .enable = ENABLE_VAL(0x0, 8, 2, 14),
140 .mdiv = REG_VAL(0x8, 10, 8),
143 .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
146 .mdiv = REG_VAL(0x8, 20, 8),
149 .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
152 .mdiv = REG_VAL(0xc, 0, 8),
155 .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
158 .mdiv = REG_VAL(0xc, 10, 8),
161 .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
164 .mdiv = REG_VAL(0xc, 20, 8),
173 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
209 .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
212 .mdiv = REG_VAL(0x20, 0, 8),
215 .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
218 .mdiv = REG_VAL(0x20, 10, 8),
221 .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
223 .enable = ENABLE_VAL(0x4, 14, 8, 20),
224 .mdiv = REG_VAL(0x20, 20, 8),
227 .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
230 .mdiv = REG_VAL(0x24, 0, 8),
233 .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
236 .mdiv = REG_VAL(0x24, 10, 8),
239 .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
242 .mdiv = REG_VAL(0x24, 20, 8),
252 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
270 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
289 .channel = BCM_CYGNUS_AUDIOPLL_CH0,
291 .enable = ENABLE_VAL(0x14, 8, 10, 9),
292 .mdiv = REG_VAL(0x14, 0, 8),
295 .channel = BCM_CYGNUS_AUDIOPLL_CH1,
297 .enable = ENABLE_VAL(0x18, 8, 10, 9),
298 .mdiv = REG_VAL(0x18, 0, 8),
301 .channel = BCM_CYGNUS_AUDIOPLL_CH2,
303 .enable = ENABLE_VAL(0x1c, 8, 10, 9),
304 .mdiv = REG_VAL(0x1c, 0, 8),
313 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",