Lines Matching +full:4 +full:- +full:channel
16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
62 .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
66 .pdiv = REG_VAL(0x14, 0, 4),
73 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
79 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
85 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
91 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
97 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
99 .enable = ENABLE_VAL(0x4, 10, 4, 16),
103 .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
115 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
119 .aon = AON_VAL(0x0, 2, 5, 4),
121 .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
124 .pdiv = REG_VAL(0x4, 26, 4),
131 .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
137 .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
143 .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
149 .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
151 .enable = ENABLE_VAL(0x0, 10, 4, 16),
155 .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
161 .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
173 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
196 .aon = AON_VAL(0x0, 4, 17, 16),
199 .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
202 .pdiv = REG_VAL(0x14, 0, 4),
209 .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
215 .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
221 .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
227 .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
233 .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
239 .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
252 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
270 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
277 .dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),
281 .pdiv = REG_VAL(0x44, 0, 4),
289 .channel = BCM_CYGNUS_AUDIOPLL_CH0,
295 .channel = BCM_CYGNUS_AUDIOPLL_CH1,
301 .channel = BCM_CYGNUS_AUDIOPLL_CH2,
313 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",