Lines Matching +full:ld +full:- +full:pulse +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/clk-provider.h>
31 #include <linux/delay.h>
37 #include <dt-bindings/clock/bcm2835.h>
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
336 writel(CM_PASSWORD | val, cprman->regs + reg); in cprman_write()
341 return readl(cprman->regs + reg); in cprman_read()
354 spin_lock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
364 /* do a kind delay at the start */ in bcm2835_measure_tcnt_mux()
371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); in bcm2835_measure_tcnt_mux()
382 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); in bcm2835_measure_tcnt_mux()
394 spin_unlock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); in bcm2835_debugfs_regset()
409 regset->regs = regs; in bcm2835_debugfs_regset()
410 regset->nregs = nregs; in bcm2835_debugfs_regset()
411 regset->base = cprman->regs + base; in bcm2835_debugfs_regset()
433 * pre-divide-by-2.
523 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_is_on()
524 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_is_on()
526 return cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_is_on()
534 * On BCM2711 there isn't a pre-divisor available in the PLL feedback in bcm2835_pll_get_prediv_mask()
535 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed in bcm2835_pll_get_prediv_mask()
538 if (cprman->soc & SOC_BCM2711) in bcm2835_pll_get_prediv_mask()
541 return data->ana->fb_prediv_mask; in bcm2835_pll_get_prediv_mask()
554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); in bcm2835_pll_choose_ndiv_and_fdiv()
574 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_round_rate()
577 rate = clamp(rate, data->min_rate, data->max_rate); in bcm2835_pll_round_rate()
588 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_get_rate()
589 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_get_rate()
590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_get_rate()
597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; in bcm2835_pll_get_rate()
600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & in bcm2835_pll_get_rate()
614 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_off()
615 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_off()
617 spin_lock(&cprman->regs_lock); in bcm2835_pll_off()
618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); in bcm2835_pll_off()
619 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_off()
620 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_off()
622 spin_unlock(&cprman->regs_lock); in bcm2835_pll_off()
628 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_on()
629 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_on()
632 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
633 cprman_read(cprman, data->a2w_ctrl_reg) & in bcm2835_pll_on()
637 spin_lock(&cprman->regs_lock); in bcm2835_pll_on()
638 cprman_write(cprman, data->cm_ctrl_reg, in bcm2835_pll_on()
639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); in bcm2835_pll_on()
640 spin_unlock(&cprman->regs_lock); in bcm2835_pll_on()
644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { in bcm2835_pll_on()
646 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_pll_on()
648 return -ETIMEDOUT; in bcm2835_pll_on()
654 cprman_write(cprman, data->a2w_ctrl_reg, in bcm2835_pll_on()
655 cprman_read(cprman, data->a2w_ctrl_reg) | in bcm2835_pll_on()
668 * ANA3-ANA0, in that order. This lets us write all 4 in bcm2835_pll_write_ana()
671 * 3 individually through their partial-write registers, each in bcm2835_pll_write_ana()
674 for (i = 3; i >= 0; i--) in bcm2835_pll_write_ana()
682 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_set_rate()
683 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_set_rate()
690 if (rate > data->max_fb_rate) { in bcm2835_pll_set_rate()
699 for (i = 3; i >= 0; i--) in bcm2835_pll_set_rate()
700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); in bcm2835_pll_set_rate()
704 ana[0] &= ~data->ana->mask0; in bcm2835_pll_set_rate()
705 ana[0] |= data->ana->set0; in bcm2835_pll_set_rate()
706 ana[1] &= ~data->ana->mask1; in bcm2835_pll_set_rate()
707 ana[1] |= data->ana->set1; in bcm2835_pll_set_rate()
708 ana[3] &= ~data->ana->mask3; in bcm2835_pll_set_rate()
709 ana[3] |= data->ana->set3; in bcm2835_pll_set_rate()
722 spin_lock(&cprman->regs_lock); in bcm2835_pll_set_rate()
725 data->reference_enable_mask); in bcm2835_pll_set_rate()
726 spin_unlock(&cprman->regs_lock); in bcm2835_pll_set_rate()
729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
732 cprman_write(cprman, data->frac_reg, fdiv); in bcm2835_pll_set_rate()
734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); in bcm2835_pll_set_rate()
739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); in bcm2835_pll_set_rate()
742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); in bcm2835_pll_set_rate()
751 struct bcm2835_cprman *cprman = pll->cprman; in bcm2835_pll_debug_init()
752 const struct bcm2835_pll_data *data = pll->data; in bcm2835_pll_debug_init()
755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_debug_init()
760 regs[0].offset = data->cm_ctrl_reg; in bcm2835_pll_debug_init()
762 regs[1].offset = data->a2w_ctrl_reg; in bcm2835_pll_debug_init()
764 regs[2].offset = data->frac_reg; in bcm2835_pll_debug_init()
766 regs[3].offset = data->ana_reg_base + 0 * 4; in bcm2835_pll_debug_init()
768 regs[4].offset = data->ana_reg_base + 1 * 4; in bcm2835_pll_debug_init()
770 regs[5].offset = data->ana_reg_base + 2 * 4; in bcm2835_pll_debug_init()
772 regs[6].offset = data->ana_reg_base + 3 * 4; in bcm2835_pll_debug_init()
802 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_is_on()
803 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_is_on()
805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); in bcm2835_pll_divider_is_on()
824 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_off()
825 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_off()
827 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_off()
828 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_off()
829 (cprman_read(cprman, data->cm_reg) & in bcm2835_pll_divider_off()
830 ~data->load_mask) | data->hold_mask); in bcm2835_pll_divider_off()
831 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_off()
832 cprman_read(cprman, data->a2w_reg) | in bcm2835_pll_divider_off()
834 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_off()
840 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_on()
841 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_on()
843 spin_lock(&cprman->regs_lock); in bcm2835_pll_divider_on()
844 cprman_write(cprman, data->a2w_reg, in bcm2835_pll_divider_on()
845 cprman_read(cprman, data->a2w_reg) & in bcm2835_pll_divider_on()
848 cprman_write(cprman, data->cm_reg, in bcm2835_pll_divider_on()
849 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); in bcm2835_pll_divider_on()
850 spin_unlock(&cprman->regs_lock); in bcm2835_pll_divider_on()
860 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_set_rate()
861 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_set_rate()
870 cprman_write(cprman, data->a2w_reg, div); in bcm2835_pll_divider_set_rate()
871 cm = cprman_read(cprman, data->cm_reg); in bcm2835_pll_divider_set_rate()
872 cprman_write(cprman, data->cm_reg, cm | data->load_mask); in bcm2835_pll_divider_set_rate()
873 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); in bcm2835_pll_divider_set_rate()
882 struct bcm2835_cprman *cprman = divider->cprman; in bcm2835_pll_divider_debug_init()
883 const struct bcm2835_pll_divider_data *data = divider->data; in bcm2835_pll_divider_debug_init()
886 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL); in bcm2835_pll_divider_debug_init()
891 regs[0].offset = data->cm_reg; in bcm2835_pll_divider_debug_init()
893 regs[1].offset = data->a2w_reg; in bcm2835_pll_divider_debug_init()
909 * The CM dividers do fixed-point division, so we can't use the
912 * because we'd run out of bits in a 32-bit unsigned long).
928 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_is_on()
929 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_is_on()
931 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on()
940 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div()
942 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; in bcm2835_clock_choose_div()
956 if (data->is_mash_clock) { in bcm2835_clock_choose_div()
960 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; in bcm2835_clock_choose_div()
965 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, in bcm2835_clock_choose_div()
966 CM_DIV_FRAC_BITS - data->frac_bits); in bcm2835_clock_choose_div()
980 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_rate_from_divisor()
983 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_rate_from_divisor()
990 div >>= CM_DIV_FRAC_BITS - data->frac_bits; in bcm2835_clock_rate_from_divisor()
991 div &= (1 << (data->int_bits + data->frac_bits)) - 1; in bcm2835_clock_rate_from_divisor()
996 temp = (u64)parent_rate << data->frac_bits; in bcm2835_clock_rate_from_divisor()
1007 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_rate()
1008 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_rate()
1011 if (data->int_bits == 0 && data->frac_bits == 0) in bcm2835_clock_get_rate()
1014 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1021 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_wait_busy()
1022 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_wait_busy()
1025 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy()
1027 dev_err(cprman->dev, "%s: couldn't lock PLL\n", in bcm2835_clock_wait_busy()
1028 clk_hw_get_name(&clock->hw)); in bcm2835_clock_wait_busy()
1038 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_off()
1039 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_off()
1041 spin_lock(&cprman->regs_lock); in bcm2835_clock_off()
1042 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off()
1043 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off()
1044 spin_unlock(&cprman->regs_lock); in bcm2835_clock_off()
1053 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_on()
1054 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_on()
1056 spin_lock(&cprman->regs_lock); in bcm2835_clock_on()
1057 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on()
1058 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on()
1061 spin_unlock(&cprman->regs_lock); in bcm2835_clock_on()
1066 if (data->tcnt_mux && false) { in bcm2835_clock_on()
1067 dev_info(cprman->dev, in bcm2835_clock_on()
1068 "clk %s: rate %ld, measure %ld\n", in bcm2835_clock_on()
1069 data->name, in bcm2835_clock_on()
1071 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); in bcm2835_clock_on()
1081 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_rate()
1082 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_rate()
1086 spin_lock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1094 * clk-framework. in bcm2835_clock_set_rate()
1096 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate()
1098 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate()
1100 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1102 spin_unlock(&cprman->regs_lock); in bcm2835_clock_set_rate()
1124 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_choose_div_and_prate()
1125 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_choose_div_and_prate()
1132 if (!(BIT(parent_idx) & data->set_rate_parent)) { in bcm2835_clock_choose_div_and_prate()
1138 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) { in bcm2835_clock_choose_div_and_prate()
1152 return *avgrate - max(*avgrate - low, high - *avgrate); in bcm2835_clock_choose_div_and_prate()
1157 if (data->frac_bits) in bcm2835_clock_choose_div_and_prate()
1158 dev_warn(cprman->dev, in bcm2835_clock_choose_div_and_prate()
1162 mindiv = data->is_mash_clock ? 2 : 1; in bcm2835_clock_choose_div_and_prate()
1163 maxdiv = BIT(data->int_bits) - 1; in bcm2835_clock_choose_div_and_prate()
1208 * Don't choose a PLLC-derived clock as our parent in bcm2835_clock_determine_rate()
1211 * over-temp or under-voltage conditions, without in bcm2835_clock_determine_rate()
1217 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, in bcm2835_clock_determine_rate()
1220 if (rate > best_rate && rate <= req->rate) { in bcm2835_clock_determine_rate()
1229 return -EINVAL; in bcm2835_clock_determine_rate()
1231 req->best_parent_hw = best_parent; in bcm2835_clock_determine_rate()
1232 req->best_parent_rate = best_prate; in bcm2835_clock_determine_rate()
1234 req->rate = best_avgrate; in bcm2835_clock_determine_rate()
1242 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_set_parent()
1243 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_set_parent()
1246 cprman_write(cprman, data->ctl_reg, src); in bcm2835_clock_set_parent()
1253 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_get_parent()
1254 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_get_parent()
1255 u32 src = cprman_read(cprman, data->ctl_reg); in bcm2835_clock_get_parent()
1275 struct bcm2835_cprman *cprman = clock->cprman; in bcm2835_clock_debug_init()
1276 const struct bcm2835_clock_data *data = clock->data; in bcm2835_clock_debug_init()
1278 bcm2835_debugfs_regset(cprman, data->ctl_reg, in bcm2835_clock_debug_init()
1326 init.parent_names = &cprman->real_parent_names[0]; in bcm2835_register_pll()
1328 init.name = pll_data->name; in bcm2835_register_pll()
1330 init.flags = pll_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll()
1336 pll->cprman = cprman; in bcm2835_register_pll()
1337 pll->data = pll_data; in bcm2835_register_pll()
1338 pll->hw.init = &init; in bcm2835_register_pll()
1340 ret = devm_clk_hw_register(cprman->dev, &pll->hw); in bcm2835_register_pll()
1345 return &pll->hw; in bcm2835_register_pll()
1358 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1359 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, in bcm2835_register_pll_divider()
1360 "%s_prediv", divider_data->name); in bcm2835_register_pll_divider()
1364 divider_name = divider_data->name; in bcm2835_register_pll_divider()
1369 init.parent_names = ÷r_data->source_pll; in bcm2835_register_pll_divider()
1373 init.flags = divider_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_pll_divider()
1375 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); in bcm2835_register_pll_divider()
1379 divider->div.reg = cprman->regs + divider_data->a2w_reg; in bcm2835_register_pll_divider()
1380 divider->div.shift = A2W_PLL_DIV_SHIFT; in bcm2835_register_pll_divider()
1381 divider->div.width = A2W_PLL_DIV_BITS; in bcm2835_register_pll_divider()
1382 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; in bcm2835_register_pll_divider()
1383 divider->div.lock = &cprman->regs_lock; in bcm2835_register_pll_divider()
1384 divider->div.hw.init = &init; in bcm2835_register_pll_divider()
1385 divider->div.table = NULL; in bcm2835_register_pll_divider()
1387 divider->cprman = cprman; in bcm2835_register_pll_divider()
1388 divider->data = divider_data; in bcm2835_register_pll_divider()
1390 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); in bcm2835_register_pll_divider()
1398 if (divider_data->fixed_divider != 1) { in bcm2835_register_pll_divider()
1399 return clk_hw_register_fixed_factor(cprman->dev, in bcm2835_register_pll_divider()
1400 divider_data->name, in bcm2835_register_pll_divider()
1404 divider_data->fixed_divider); in bcm2835_register_pll_divider()
1407 return ÷r->div.hw; in bcm2835_register_pll_divider()
1422 * actual clock-output-name of the parent. in bcm2835_register_clock()
1424 for (i = 0; i < clock_data->num_mux_parents; i++) { in bcm2835_register_clock()
1425 parents[i] = clock_data->parents[i]; in bcm2835_register_clock()
1431 parents[i] = cprman->real_parent_names[ret]; in bcm2835_register_clock()
1436 init.num_parents = clock_data->num_mux_parents; in bcm2835_register_clock()
1437 init.name = clock_data->name; in bcm2835_register_clock()
1438 init.flags = clock_data->flags | CLK_IGNORE_UNUSED; in bcm2835_register_clock()
1444 if (clock_data->set_rate_parent) in bcm2835_register_clock()
1447 if (clock_data->is_vpu_clock) { in bcm2835_register_clock()
1456 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE)) in bcm2835_register_clock()
1460 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); in bcm2835_register_clock()
1464 clock->cprman = cprman; in bcm2835_register_clock()
1465 clock->data = clock_data; in bcm2835_register_clock()
1466 clock->hw.init = &init; in bcm2835_register_clock()
1468 ret = devm_clk_hw_register(cprman->dev, &clock->hw); in bcm2835_register_clock()
1471 return &clock->hw; in bcm2835_register_clock()
1479 return clk_hw_register_gate(cprman->dev, gate_data->name, in bcm2835_register_gate()
1480 gate_data->parent, in bcm2835_register_gate()
1482 cprman->regs + gate_data->ctl_reg, in bcm2835_register_gate()
1483 CM_GATE_BIT, 0, &cprman->regs_lock); in bcm2835_register_gate()
1558 "-",
1560 "-",
1561 "-",
1562 "-",
1563 "-",
1565 "-",
1928 * bythe watchdog timer and the camera pulse generator.
1975 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
2210 * non-stop vpu clock.
2240 struct device *dev = &pdev->dev; in bcm2835_clk_probe()
2249 pdata = of_device_get_match_data(&pdev->dev); in bcm2835_clk_probe()
2251 return -ENODEV; in bcm2835_clk_probe()
2257 return -ENOMEM; in bcm2835_clk_probe()
2259 spin_lock_init(&cprman->regs_lock); in bcm2835_clk_probe()
2260 cprman->dev = dev; in bcm2835_clk_probe()
2261 cprman->regs = devm_platform_ioremap_resource(pdev, 0); in bcm2835_clk_probe()
2262 if (IS_ERR(cprman->regs)) in bcm2835_clk_probe()
2263 return PTR_ERR(cprman->regs); in bcm2835_clk_probe()
2265 memcpy(cprman->real_parent_names, cprman_parent_names, in bcm2835_clk_probe()
2267 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, in bcm2835_clk_probe()
2277 if (!cprman->real_parent_names[0]) in bcm2835_clk_probe()
2278 return -ENODEV; in bcm2835_clk_probe()
2282 cprman->onecell.num = asize; in bcm2835_clk_probe()
2283 cprman->soc = pdata->soc; in bcm2835_clk_probe()
2284 hws = cprman->onecell.hws; in bcm2835_clk_probe()
2288 if (desc->clk_register && desc->data && in bcm2835_clk_probe()
2289 (desc->supported & pdata->soc)) { in bcm2835_clk_probe()
2290 hws[i] = desc->clk_register(cprman, desc->data); in bcm2835_clk_probe()
2294 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); in bcm2835_clk_probe()
2298 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, in bcm2835_clk_probe()
2299 &cprman->onecell); in bcm2835_clk_probe()
2311 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2312 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2319 .name = "bcm2835-clk",