86  * register_mutex is endpoint-specific, and is held when non-atomic
101 static void malformed_message(struct xilly_endpoint *endpoint, u32 *buf)  in malformed_message()  argument
112 	dev_warn(endpoint->dev,  in malformed_message()
474 		channel->endpoint = ep;  in xilly_setupchannels()
564 static int xilly_scan_idt(struct xilly_endpoint *endpoint,  in xilly_scan_idt()  argument
568 	unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr;  in xilly_scan_idt()
569 	unsigned char *end_of_idt = idt + endpoint->idtlen - 4;  in xilly_scan_idt()
587 		dev_err(endpoint->dev,  in xilly_scan_idt()
593 	len = endpoint->idtlen - (3 + ((int) (scan - idt)));  in xilly_scan_idt()
596 		dev_err(endpoint->dev,  in xilly_scan_idt()
602 	endpoint->num_channels = count;  in xilly_scan_idt()
607 static int xilly_obtain_idt(struct xilly_endpoint *endpoint)  in xilly_obtain_idt()  argument
613 	channel = endpoint->channels[1]; /* This should be generated ad-hoc */  in xilly_obtain_idt()
619 		  endpoint->registers + fpga_buf_ctrl_reg);  in xilly_obtain_idt()
626 		dev_err(endpoint->dev, "Failed to obtain IDT. Aborting.\n");  in xilly_obtain_idt()
628 		if (endpoint->fatal_error)  in xilly_obtain_idt()
634 	endpoint->ephw->hw_sync_sgl_for_cpu(  in xilly_obtain_idt()
635 		channel->endpoint,  in xilly_obtain_idt()
640 	if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) {  in xilly_obtain_idt()
641 		dev_err(endpoint->dev,  in xilly_obtain_idt()
643 			channel->wr_buffers[0]->end_offset, endpoint->idtlen);  in xilly_obtain_idt()
648 		     endpoint->idtlen+1) != 0) {  in xilly_obtain_idt()
649 		dev_err(endpoint->dev, "IDT failed CRC check. Aborting.\n");  in xilly_obtain_idt()
657 		dev_err(endpoint->dev,  in xilly_obtain_idt()
682 	if (channel->endpoint->fatal_error)  in xillybus_read()
749 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_read()
750 					channel->endpoint,  in xillybus_read()
765 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_read()
766 					channel->endpoint,  in xillybus_read()
781 					  channel->endpoint->registers +  in xillybus_read()
863 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_read()
866 					  channel->endpoint->registers +  in xillybus_read()
872 					  channel->endpoint->registers +  in xillybus_read()
875 				mutex_unlock(&channel->endpoint->  in xillybus_read()
910 			if (channel->endpoint->fatal_error)  in xillybus_read()
939 				if (channel->endpoint->fatal_error)  in xillybus_read()
961 				  channel->endpoint->registers +  in xillybus_read()
976 	if (channel->endpoint->fatal_error)  in xillybus_read()
1003 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1069 		channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_myflush()
1070 			channel->endpoint,  in xillybus_myflush()
1075 		mutex_lock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1078 			  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_myflush()
1083 			  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_myflush()
1085 		mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_myflush()
1134 			dev_warn(channel->endpoint->dev,  in xillybus_myflush()
1150 	if (channel->endpoint->fatal_error)  in xillybus_myflush()
1174 		dev_warn(channel->endpoint->dev,  in xillybus_autoflush()
1177 		dev_err(channel->endpoint->dev,  in xillybus_autoflush()
1195 	if (channel->endpoint->fatal_error)  in xillybus_write()
1289 				channel->endpoint->ephw->hw_sync_sgl_for_cpu(  in xillybus_write()
1290 					channel->endpoint,  in xillybus_write()
1311 				channel->endpoint->ephw->hw_sync_sgl_for_device(  in xillybus_write()
1312 					channel->endpoint,  in xillybus_write()
1317 				mutex_lock(&channel->endpoint->register_mutex);  in xillybus_write()
1320 					  channel->endpoint->registers +  in xillybus_write()
1326 					  channel->endpoint->registers +  in xillybus_write()
1329 				mutex_unlock(&channel->endpoint->  in xillybus_write()
1339 				if (channel->endpoint->fatal_error)  in xillybus_write()
1376 			if (channel->endpoint->fatal_error)  in xillybus_write()
1392 	if (channel->endpoint->fatal_error)  in xillybus_write()
1414 	struct xilly_endpoint *ep_iter, *endpoint = NULL;  in xillybus_open()  local
1424 			endpoint = ep_iter;  in xillybus_open()
1430 	if (!endpoint) {  in xillybus_open()
1436 	if (endpoint->fatal_error)  in xillybus_open()
1439 	channel = endpoint->channels[1 + minor - endpoint->lowest_minor];  in xillybus_open()
1457 		dev_err(endpoint->dev,  in xillybus_open()
1464 		dev_err(endpoint->dev,  in xillybus_open()
1520 				  channel->endpoint->registers +  in xillybus_open()
1541 				  channel->endpoint->registers +  in xillybus_open()
1569 	if (channel->endpoint->fatal_error)  in xillybus_release()
1585 				  channel->endpoint->registers +  in xillybus_release()
1599 				  channel->endpoint->registers +  in xillybus_release()
1649 					dev_warn(channel->endpoint->dev,  in xillybus_release()
1675 	if (channel->endpoint->fatal_error)  in xillybus_llseek()
1702 	mutex_lock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1705 		  channel->endpoint->registers + fpga_buf_offset_reg);  in xillybus_llseek()
1709 		  channel->endpoint->registers + fpga_buf_ctrl_reg);  in xillybus_llseek()
1711 	mutex_unlock(&channel->endpoint->register_mutex);  in xillybus_llseek()
1742 	poll_wait(filp, &channel->endpoint->ep_wait, wait);  in xillybus_poll()
1785 	if (channel->endpoint->fatal_error)  in xillybus_poll()
1802 static int xillybus_init_chrdev(struct xilly_endpoint *endpoint,  in xillybus_init_chrdev()  argument
1812 				 endpoint->num_channels,  in xillybus_init_chrdev()
1815 		dev_warn(endpoint->dev, "Failed to obtain major/minors");  in xillybus_init_chrdev()
1819 	endpoint->major = major = MAJOR(dev);  in xillybus_init_chrdev()
1820 	endpoint->lowest_minor = minor = MINOR(dev);  in xillybus_init_chrdev()
1822 	cdev_init(&endpoint->cdev, &xillybus_fops);  in xillybus_init_chrdev()
1823 	endpoint->cdev.owner = endpoint->ephw->owner;  in xillybus_init_chrdev()
1824 	rc = cdev_add(&endpoint->cdev, MKDEV(major, minor),  in xillybus_init_chrdev()
1825 		      endpoint->num_channels);  in xillybus_init_chrdev()
1827 		dev_warn(endpoint->dev, "Failed to add cdev. Aborting.\n");  in xillybus_init_chrdev()
1834 	     devnum < endpoint->num_channels;  in xillybus_init_chrdev()
1850 			dev_warn(endpoint->dev,  in xillybus_init_chrdev()
1858 	dev_info(endpoint->dev, "Created %d device files.\n",  in xillybus_init_chrdev()
1859 		 endpoint->num_channels);  in xillybus_init_chrdev()
1867 	cdev_del(&endpoint->cdev);  in xillybus_init_chrdev()
1869 	unregister_chrdev_region(MKDEV(major, minor), endpoint->num_channels);  in xillybus_init_chrdev()
1874 static void xillybus_cleanup_chrdev(struct xilly_endpoint *endpoint)  in xillybus_cleanup_chrdev()  argument
1878 	for (minor = endpoint->lowest_minor;  in xillybus_cleanup_chrdev()
1879 	     minor < (endpoint->lowest_minor + endpoint->num_channels);  in xillybus_cleanup_chrdev()
1881 		device_destroy(xillybus_class, MKDEV(endpoint->major, minor));  in xillybus_cleanup_chrdev()
1882 	cdev_del(&endpoint->cdev);  in xillybus_cleanup_chrdev()
1883 	unregister_chrdev_region(MKDEV(endpoint->major,  in xillybus_cleanup_chrdev()
1884 				       endpoint->lowest_minor),  in xillybus_cleanup_chrdev()
1885 				 endpoint->num_channels);  in xillybus_cleanup_chrdev()
1887 	dev_info(endpoint->dev, "Removed %d device files.\n",  in xillybus_cleanup_chrdev()
1888 		 endpoint->num_channels);  in xillybus_cleanup_chrdev()
1896 	struct xilly_endpoint *endpoint;  in xillybus_init_endpoint()  local
1898 	endpoint = devm_kzalloc(dev, sizeof(*endpoint), GFP_KERNEL);  in xillybus_init_endpoint()
1899 	if (!endpoint)  in xillybus_init_endpoint()
1902 	endpoint->pdev = pdev;  in xillybus_init_endpoint()
1903 	endpoint->dev = dev;  in xillybus_init_endpoint()
1904 	endpoint->ephw = ephw;  in xillybus_init_endpoint()
1905 	endpoint->msg_counter = 0x0b;  in xillybus_init_endpoint()
1906 	endpoint->failed_messages = 0;  in xillybus_init_endpoint()
1907 	endpoint->fatal_error = 0;  in xillybus_init_endpoint()
1909 	init_waitqueue_head(&endpoint->ep_wait);  in xillybus_init_endpoint()
1910 	mutex_init(&endpoint->register_mutex);  in xillybus_init_endpoint()
1912 	return endpoint;  in xillybus_init_endpoint()
1916 static int xilly_quiesce(struct xilly_endpoint *endpoint)  in xilly_quiesce()  argument
1920 	endpoint->idtlen = -1;  in xilly_quiesce()
1922 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xilly_quiesce()
1923 		  endpoint->registers + fpga_dma_control_reg);  in xilly_quiesce()
1925 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xilly_quiesce()
1926 					     (endpoint->idtlen >= 0),  in xilly_quiesce()
1929 		dev_err(endpoint->dev,  in xilly_quiesce()
1936 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)  in xillybus_endpoint_discovery()  argument
1943 	struct device *dev = endpoint->dev;  in xillybus_endpoint_discovery()
1962 	iowrite32(1, endpoint->registers + fpga_endian_reg);  in xillybus_endpoint_discovery()
1970 	endpoint->num_channels = 0;  in xillybus_endpoint_discovery()
1972 	rc = xilly_setupchannels(endpoint, bogus_idt, 1);  in xillybus_endpoint_discovery()
1977 	iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);  in xillybus_endpoint_discovery()
1979 	endpoint->idtlen = -1;  in xillybus_endpoint_discovery()
1985 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xillybus_endpoint_discovery()
1986 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
1988 	t = wait_event_interruptible_timeout(endpoint->ep_wait,  in xillybus_endpoint_discovery()
1989 					     (endpoint->idtlen >= 0),  in xillybus_endpoint_discovery()
1992 		dev_err(endpoint->dev, "No response from FPGA. Aborting.\n");  in xillybus_endpoint_discovery()
1997 	iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),  in xillybus_endpoint_discovery()
1998 		  endpoint->registers + fpga_dma_control_reg);  in xillybus_endpoint_discovery()
2001 	while (endpoint->idtlen >= idtbuffersize) {  in xillybus_endpoint_discovery()
2006 	endpoint->num_channels = 1;  in xillybus_endpoint_discovery()
2008 	rc = xilly_setupchannels(endpoint, bogus_idt, 2);  in xillybus_endpoint_discovery()
2012 	rc = xilly_obtain_idt(endpoint);  in xillybus_endpoint_discovery()
2016 	rc = xilly_scan_idt(endpoint, &idt_handle);  in xillybus_endpoint_discovery()
2024 	rc = xilly_setupchannels(endpoint,  in xillybus_endpoint_discovery()
2031 	 * endpoint is now completely configured. We put it on the list  in xillybus_endpoint_discovery()
2036 	list_add_tail(&endpoint->ep_list, &list_of_endpoints);  in xillybus_endpoint_discovery()
2039 	rc = xillybus_init_chrdev(endpoint, idt_handle.idt);  in xillybus_endpoint_discovery()
2049 	list_del(&endpoint->ep_list);  in xillybus_endpoint_discovery()
2053 	xilly_quiesce(endpoint);  in xillybus_endpoint_discovery()
2060 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint)  in xillybus_endpoint_remove()  argument
2062 	xillybus_cleanup_chrdev(endpoint);  in xillybus_endpoint_remove()
2065 	list_del(&endpoint->ep_list);  in xillybus_endpoint_remove()
2068 	xilly_quiesce(endpoint);  in xillybus_endpoint_remove()
2071 	 * Flushing is done upon endpoint release to prevent access to memory  in xillybus_endpoint_remove()
2097 	/* flush_workqueue() was called for each endpoint released */  in xillybus_exit()