Lines Matching defs:xilly_channel

43 struct xilly_channel {  struct
44 	struct xilly_endpoint *endpoint;
45 	int chan_num;
46 	int log2_element_size;
47 	int seekable;
49 	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
50 	int num_wr_buffers;
51 	unsigned int wr_buf_size; /* In bytes */
52 	int wr_fpga_buf_idx;
53 	int wr_host_buf_idx;
54 	int wr_host_buf_pos;
55 	int wr_empty;
56 	int wr_ready; /* Significant only when wr_empty == 1 */
57 	int wr_sleepy;
58 	int wr_eof;
59 	int wr_hangup;
60 	spinlock_t wr_spinlock;
61 	struct mutex wr_mutex;
62 	wait_queue_head_t wr_wait;
63 	wait_queue_head_t wr_ready_wait;
64 	int wr_ref_count;
65 	int wr_synchronous;
66 	int wr_allow_partial;
67 	int wr_exclusive_open;
68 	int wr_supports_nonempty;
70 	struct xilly_buffer **rd_buffers; /* FPGA reads, driver writes! */
71 	int num_rd_buffers;
72 	unsigned int rd_buf_size; /* In bytes */
73 	int rd_fpga_buf_idx;
74 	int rd_host_buf_pos;
75 	int rd_host_buf_idx;
76 	int rd_full;
77 	spinlock_t rd_spinlock;
78 	struct mutex rd_mutex;
79 	wait_queue_head_t rd_wait;
80 	int rd_ref_count;
81 	int rd_allow_partial;
82 	int rd_synchronous;
83 	int rd_exclusive_open;
84 	struct delayed_work rd_workitem;
85 	unsigned char rd_leftovers[4];