493 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_dma_prep()
528 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_nodata_prep()
561 	readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in __pdc20621_push_hdma()
564 	readl(mmio + PDC_HDMA_PKT_SUBMIT);	/* flush */  in __pdc20621_push_hdma()
614 	printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));  in pdc20621_dump_hdma()
615 	printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));  in pdc20621_dump_hdma()
616 	printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));  in pdc20621_dump_hdma()
617 	printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));  in pdc20621_dump_hdma()
654 		readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in pdc20621_packet_start()
658 		readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_packet_start()
707 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
718 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
733 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
737 			readl(mmio + PDC_20621_SEQCTL + (seq * 4));  in pdc20621_host_intr()
740 			readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_host_intr()
746 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
795 	mask = readl(mmio_base + PDC_20621_SEQMASK);  in pdc20621_interrupt()
846 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_freeze()
850 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_freeze()
864 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_thaw()
867 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_thaw()
879 		tmp = readl(mmio);  in pdc_reset_port()
891 	readl(mmio);	/* flush */  in pdc_reset_port()
1001 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1003 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1015 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1017 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1026 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1028 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1053 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1060 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1066 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1069 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1077 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1080 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1101 	readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1108 		status = readl(mmio + PDC_I2C_CONTROL);  in pdc20621_i2c_read()
1110 			status = readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1201 	readl(mmio + PDC_DIMM0_CONTROL);  in pdc20621_prog_dimm0()
1224 	readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1236 		readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1247 		data = readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1276 	time_period = readl(mmio + PDC_TIME_PERIOD);  in pdc20621_dimm_init()
1281 	readl(mmio + PDC_TIME_CONTROL);  in pdc20621_dimm_init()
1291 	tcount = readl(mmio + PDC_TIME_COUNTER);  in pdc20621_dimm_init()
1320 	readl(mmio + PDC_CTL_STATUS);  in pdc20621_dimm_init()
1410 	tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;  in pdc_20621_init()
1417 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1420 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()
1424 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1427 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()