35 	USE_DPLL	=	(1 << 0)
50  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
59  * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
73 	{	XFER_UDMA_7,	0x1c869c62	},
74 	{	XFER_UDMA_6,	0x1c869c62	},
75 	{	XFER_UDMA_5,	0x1c8a9c62	},
76 	{	XFER_UDMA_4,	0x1c8a9c62	},
77 	{	XFER_UDMA_3,	0x1c8e9c62	},
78 	{	XFER_UDMA_2,	0x1c929c62	},
79 	{	XFER_UDMA_1,	0x1c9a9c62	},
80 	{	XFER_UDMA_0,	0x1c829c62	},
82 	{	XFER_MW_DMA_2,	0x2c829c62	},
83 	{	XFER_MW_DMA_1,	0x2c829c66	},
84 	{	XFER_MW_DMA_0,	0x2c829d2e	},
86 	{	XFER_PIO_4,	0x0c829c62	},
87 	{	XFER_PIO_3,	0x0c829c84	},
88 	{	XFER_PIO_2,	0x0c829ca6	},
89 	{	XFER_PIO_1,	0x0d029d26	},
90 	{	XFER_PIO_0,	0x0d029d5e	},
114 	return 0xffffffffU;	/* silence compiler warning */  in hpt3x2n_find_mode()
128 		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);  in hpt372n_filter()
145 	pci_read_config_byte(pdev, 0x5B, &scr2);  in hpt3x2n_cable_detect()
146 	pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);  in hpt3x2n_cable_detect()
151 	pci_read_config_byte(pdev, 0x5A, &ata66);  in hpt3x2n_cable_detect()
153 	pci_write_config_byte(pdev, 0x5B, scr2);  in hpt3x2n_cable_detect()
176 	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);  in hpt3x2n_pre_reset()
190 	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);  in hpt3x2n_set_mode()
191 	addr2 = 0x51 + 4 * ap->port_no;  in hpt3x2n_set_mode()
195 	fast &= ~0x07;  in hpt3x2n_set_mode()
200 		mask = 0xcfc3ffff;  in hpt3x2n_set_mode()
202 		mask = 0x31c001ff;  in hpt3x2n_set_mode()
204 		mask = 0x303c0000;  in hpt3x2n_set_mode()
250 	int mscreg = 0x50 + 2 * ap->port_no;  in hpt3x2n_bmdma_stop()
253 	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);  in hpt3x2n_bmdma_stop()
256 		pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);  in hpt3x2n_bmdma_stop()
263  *	@source: 0x21 or 0x23 for PLL or PCI sourced clock
281 	iowrite8(0x80, bmdma+0x73);  in hpt3x2n_set_clock()
282 	iowrite8(0x80, bmdma+0x77);  in hpt3x2n_set_clock()
285 	iowrite8(source, bmdma+0x7B);  in hpt3x2n_set_clock()
286 	iowrite8(0xC0, bmdma+0x79);  in hpt3x2n_set_clock()
289 	iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);  in hpt3x2n_set_clock()
290 	iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);  in hpt3x2n_set_clock()
293 	iowrite8(0x00, bmdma+0x79);  in hpt3x2n_set_clock()
296 	iowrite8(0x00, bmdma+0x73);  in hpt3x2n_set_clock()
297 	iowrite8(0x00, bmdma+0x77);  in hpt3x2n_set_clock()
309 	return 0;  in hpt3x2n_use_dpll()
321 	if (rc != 0)  in hpt3x2n_qc_defer()
326 	return 0;  in hpt3x2n_qc_defer()
340 		hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);  in hpt3x2n_qc_issue()
390 	for (tries = 0; tries < 0x5000; tries++) {  in hpt3xn_calibrate_dpll()
392 		pci_read_config_byte(dev, 0x5b, &reg5b);  in hpt3xn_calibrate_dpll()
393 		if (reg5b & 0x80) {  in hpt3xn_calibrate_dpll()
395 			for (tries = 0; tries < 0x1000; tries++) {  in hpt3xn_calibrate_dpll()
396 				pci_read_config_byte(dev, 0x5b, &reg5b);  in hpt3xn_calibrate_dpll()
398 				if ((reg5b & 0x80) == 0)  in hpt3xn_calibrate_dpll()
399 					return 0;  in hpt3xn_calibrate_dpll()
402 			pci_read_config_dword(dev, 0x5c, &reg5c);  in hpt3xn_calibrate_dpll()
403 			pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);  in hpt3xn_calibrate_dpll()
408 	return 0;  in hpt3xn_calibrate_dpll()
417 	fcnt = inl(iobase + 0x90);	/* Not PCI readable for some chips */  in hpt3x2n_pci_clock()
418 	if ((fcnt >> 12) != 0xABCDE) {  in hpt3x2n_pci_clock()
421 		u32 total = 0;  in hpt3x2n_pci_clock()
426 		for (i = 0; i < 128; i++) {  in hpt3x2n_pci_clock()
427 			pci_read_config_word(pdev, 0x78, &sr);  in hpt3x2n_pci_clock()
428 			total += sr & 0x1FF;  in hpt3x2n_pci_clock()
433 	fcnt &= 0x1FF;  in hpt3x2n_pci_clock()
530 		ppi[0] = &info_hpt372n;  in hpt3x2n_init_one()
540 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);  in hpt3x2n_init_one()
541 	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);  in hpt3x2n_init_one()
542 	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);  in hpt3x2n_init_one()
544 	pci_read_config_byte(dev, 0x5A, &irqmask);  in hpt3x2n_init_one()
545 	irqmask &= ~0x10;  in hpt3x2n_init_one()
546 	pci_write_config_byte(dev, 0x5a, irqmask);  in hpt3x2n_init_one()
556 		pci_read_config_byte(dev, 0x50, &mcr1);  in hpt3x2n_init_one()
557 		mcr1 &= ~0x04;  in hpt3x2n_init_one()
558 		pci_write_config_byte(dev, 0x50, mcr1);  in hpt3x2n_init_one()
571 	pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);  in hpt3x2n_init_one()
573 	pci_write_config_byte(dev, 0x5B, 0x21);  in hpt3x2n_init_one()
576 	for (adjust = 0; adjust < 8; adjust++) {  in hpt3x2n_init_one()
579 		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);  in hpt3x2n_init_one()
601 		outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);  in hpt3x2n_init_one()
604 	return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);  in hpt3x2n_init_one()