117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)  in imx_phy_crbit_assert()  argument
124 	crval = readl(mmio + IMX_P0PHYCR);  in imx_phy_crbit_assert()
129 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_crbit_assert()
133 		srval = readl(mmio + IMX_P0PHYSR);  in imx_phy_crbit_assert()
142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)  in imx_phy_reg_addressing()  argument
148 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_addressing()
151 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);  in imx_phy_reg_addressing()
156 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);  in imx_phy_reg_addressing()
163 static int imx_phy_reg_write(u16 val, void __iomem *mmio)  in imx_phy_reg_write()  argument
169 	writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_write()
172 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);  in imx_phy_reg_write()
177 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);  in imx_phy_reg_write()
187 		writel(crval, mmio + IMX_P0PHYCR);  in imx_phy_reg_write()
192 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);  in imx_phy_reg_write()
197 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);  in imx_phy_reg_write()
205 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)  in imx_phy_reg_read()  argument
210 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);  in imx_phy_reg_read()
215 	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;  in imx_phy_reg_read()
218 	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);  in imx_phy_reg_read()
228 	void __iomem *mmio = hpriv->mmio;  in imx_sata_phy_reset()  local
248 	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);  in imx_sata_phy_reset()
251 	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);  in imx_sata_phy_reset()
258 		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);  in imx_sata_phy_reset()
261 		ret = imx_phy_reg_read(&val, mmio);  in imx_sata_phy_reset()
280 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)  in read_adc_sum()  argument
286 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);  in read_adc_sum()
287 	imx_phy_reg_write(rtune_ctl_reg, mmio);  in read_adc_sum()
293 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);  in read_adc_sum()
295 		imx_phy_reg_read(&adc_out_reg, mmio);  in read_adc_sum()
312 		imx_phy_reg_read(&adc_out_reg, mmio);  in read_adc_sum()
336 	void __iomem *mmio = hpriv->mmio;  in sata_ahci_read_temperature()  local
340 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);  in sata_ahci_read_temperature()
341 	imx_phy_reg_write(read_sum, mmio);  in sata_ahci_read_temperature()
342 	imx_phy_reg_read(&read_sum, mmio);  in sata_ahci_read_temperature()
346 	imx_phy_reg_write(0x5A5A, mmio);  in sata_ahci_read_temperature()
347 	imx_phy_reg_read(&read_sum, mmio);  in sata_ahci_read_temperature()
351 	imx_phy_reg_write(0x1234, mmio);  in sata_ahci_read_temperature()
352 	imx_phy_reg_read(&read_sum, mmio);  in sata_ahci_read_temperature()
357 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);  in sata_ahci_read_temperature()
358 	imx_phy_reg_read(&mpll_test_reg, mmio);  in sata_ahci_read_temperature()
359 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);  in sata_ahci_read_temperature()
360 	imx_phy_reg_read(&rtune_ctl_reg, mmio);  in sata_ahci_read_temperature()
361 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);  in sata_ahci_read_temperature()
362 	imx_phy_reg_read(&dac_ctl_reg, mmio);  in sata_ahci_read_temperature()
382 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);  in sata_ahci_read_temperature()
383 	imx_phy_reg_write(mpll_test_reg, mmio);  in sata_ahci_read_temperature()
384 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);  in sata_ahci_read_temperature()
385 	imx_phy_reg_write(dac_ctl_reg, mmio);  in sata_ahci_read_temperature()
386 	m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);  in sata_ahci_read_temperature()
391 	m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);  in sata_ahci_read_temperature()
403 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);  in sata_ahci_read_temperature()
404 	imx_phy_reg_write(mpll_test_reg, mmio);  in sata_ahci_read_temperature()
405 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);  in sata_ahci_read_temperature()
406 	imx_phy_reg_write(dac_ctl_reg, mmio);  in sata_ahci_read_temperature()
407 	imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);  in sata_ahci_read_temperature()
408 	imx_phy_reg_write(rtune_ctl_reg, mmio);  in sata_ahci_read_temperature()
752 	void __iomem *mmio = hpriv->mmio;  in ahci_imx_error_handler()  local
769 	reg_val = readl(mmio + IMX_P0PHYCR);  in ahci_imx_error_handler()
770 	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);  in ahci_imx_error_handler()
1150 	reg_val = readl(hpriv->mmio + HOST_CAP);  in imx_ahci_probe()
1153 		writel(reg_val, hpriv->mmio + HOST_CAP);  in imx_ahci_probe()
1155 	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);  in imx_ahci_probe()
1158 		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);  in imx_ahci_probe()
1162 	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);  in imx_ahci_probe()