Lines Matching +full:0 +full:xf000
27 #define MODULE_init 0x0dec /* module in boot code */
28 #define MODULE_self_test 0x8800 /* module in self-test */
29 #define MODULE_reset 0xffff /* reinit the whole module */
31 #define MODE_mask 0xf000 /* mode bits in high nibble */
32 #define MODE_null 0x0000
33 #define MODE_test 0x2000 /* in testing mode */
34 #define MODE_status 0x8000
35 #define STAT_int 0x0001 /* running in interrupt mode */
36 #define STAT_tr_char 0x0002 /* character data to transmit */
37 #define STAT_rr_char 0x0004 /* ready to receive char data */
38 #define STAT_cmd_ready 0x0008 /* ready to accept commands */
39 #define STAT_dma_ready 0x0010 /* dma command ready */
40 #define STAT_digitized 0x0020 /* spc in digitized mode */
41 #define STAT_new_index 0x0040 /* new last index ready */
42 #define STAT_new_status 0x0080 /* new status posted */
43 #define STAT_dma_state 0x0100 /* dma state toggle */
44 #define STAT_index_valid 0x0200 /* indexs are valid */
45 #define STAT_flushing 0x0400 /* flush in progress */
46 #define STAT_self_test 0x0800 /* module in self test */
47 #define MODE_ready 0xc000 /* module ready for next phase */
48 #define READY_boot 0x0000
49 #define READY_kernel 0x0001
50 #define MODE_error 0xf000
52 #define CMD_mask 0xf000 /* mask for command nibble */
53 #define CMD_null 0x0000 /* post status */
54 #define CMD_control 0x1000 /* hard control command */
55 #define CTRL_mask 0x0F00 /* mask off control nibble */
56 #define CTRL_data 0x00FF /* mask to get data byte */
57 #define CTRL_null 0x0000 /* null control */
58 #define CTRL_vol_up 0x0100 /* increase volume */
59 #define CTRL_vol_down 0x0200 /* decrease volume */
60 #define CTRL_vol_set 0x0300 /* set volume */
61 #define CTRL_pause 0x0400 /* pause spc */
62 #define CTRL_resume 0x0500 /* resume spc clock */
63 #define CTRL_resume_spc 0x0001 /* resume spc soft pause */
64 #define CTRL_flush 0x0600 /* flush all buffers */
65 #define CTRL_int_enable 0x0700 /* enable status change ints */
66 #define CTRL_buff_free 0x0800 /* buffer remain count */
67 #define CTRL_buff_used 0x0900 /* buffer in use */
68 #define CTRL_speech 0x0a00 /* immediate speech change */
69 #define CTRL_SP_voice 0x0001 /* voice change */
70 #define CTRL_SP_rate 0x0002 /* rate change */
71 #define CTRL_SP_comma 0x0003 /* comma pause change */
72 #define CTRL_SP_period 0x0004 /* period pause change */
73 #define CTRL_SP_rate_delta 0x0005 /* delta rate change */
74 #define CTRL_SP_get_param 0x0006 /* return the desired parameter */
75 #define CTRL_last_index 0x0b00 /* get last index spoken */
76 #define CTRL_io_priority 0x0c00 /* change i/o priority */
77 #define CTRL_free_mem 0x0d00 /* get free paragraphs on module */
78 #define CTRL_get_lang 0x0e00 /* return bitmask of loaded languages */
79 #define CMD_test 0x2000 /* self-test request */
80 #define TEST_mask 0x0F00 /* isolate test field */
81 #define TEST_null 0x0000 /* no test requested */
82 #define TEST_isa_int 0x0100 /* assert isa irq */
83 #define TEST_echo 0x0200 /* make data in == data out */
84 #define TEST_seg 0x0300 /* set peek/poke segment */
85 #define TEST_off 0x0400 /* set peek/poke offset */
86 #define TEST_peek 0x0500 /* data out == *peek */
87 #define TEST_poke 0x0600 /* *peek == data in */
88 #define TEST_sub_code 0x00FF /* user defined test sub codes */
89 #define CMD_id 0x3000 /* return software id */
90 #define ID_null 0x0000 /* null id */
91 #define ID_kernel 0x0100 /* kernel code executing */
92 #define ID_boot 0x0200 /* boot code executing */
93 #define CMD_dma 0x4000 /* force a dma start */
94 #define CMD_reset 0x5000 /* reset module status */
95 #define CMD_sync 0x6000 /* kernel sync command */
96 #define CMD_char_in 0x7000 /* single character send */
97 #define CMD_char_out 0x8000 /* single character get */
98 #define CHAR_count_1 0x0100 /* one char in cmd_low */
99 #define CHAR_count_2 0x0200 /* the second in data_low */
100 #define CHAR_count_3 0x0300 /* the third in data_high */
101 #define CMD_spc_mode 0x9000 /* change spc mode */
102 #define CMD_spc_to_text 0x0100 /* set to text mode */
103 #define CMD_spc_to_digit 0x0200 /* set to digital mode */
104 #define CMD_spc_rate 0x0400 /* change spc data rate */
105 #define CMD_error 0xf000 /* severe error */
107 enum { PRIMARY_DIC = 0, USER_DIC, COMMAND_DIC, ABBREV_DIC };
109 #define DMA_single_in 0x01
110 #define DMA_single_out 0x02
111 #define DMA_buff_in 0x03
112 #define DMA_buff_out 0x04
113 #define DMA_control 0x05
114 #define DT_MEM_ALLOC 0x03
115 #define DT_SET_DIC 0x04
116 #define DT_START_TASK 0x05
117 #define DT_LOAD_MEM 0x06
118 #define DT_READ_MEM 0x07
119 #define DT_DIGITAL_IN 0x08
120 #define DMA_sync 0x06
121 #define DMA_sync_char 0x07
124 #define PROCSPEECH 0x0b
133 static int synth_portlist[] = { 0x340, 0x350, 0x240, 0x250, 0 };
140 { RATE, .u.n = {"[:ra %d]", 9, 0, 18, 150, 25, NULL } },
141 { PITCH, .u.n = {"[:dv ap %d]", 80, 0, 100, 20, 0, NULL } },
142 { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
143 { VOL, .u.n = {"[:vo se %d]", 5, 0, 9, 5, 10, NULL } },
144 { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
145 { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
146 { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
228 .lowindex = 0,
229 .highindex = 0,
230 .currindex = 0,
247 outb_p(cmd & 0xFF, speakup_info.port_tts); in dt_sendcmd()
248 outb_p((cmd >> 8) & 0xFF, speakup_info.port_tts + 1); in dt_sendcmd()
255 while (--timeout > 0) { in dt_waitbit()
260 return 0; in dt_waitbit()
268 return 0; in dt_wait_dma()
269 while (--timeout > 0) { in dt_wait_dma()
284 outb_p(0, speakup_info.port_tts + 2); in dt_ctrl()
285 outb_p(0, speakup_info.port_tts + 3); in dt_ctrl()
288 outb_p(0, speakup_info.port_tts + 6); in dt_ctrl()
291 if (--timeout == 0) in dt_ctrl()
295 return 0; in dt_ctrl()
305 in_escape = 0; in synth_flush()
307 if (--timeout == 0) in synth_flush()
311 for (timeout = 0; timeout < 10; timeout++) { in synth_flush()
317 outb_p(0, speakup_info.port_tts + 4); in synth_flush()
319 for (timeout = 0; timeout < 10; timeout++) { in synth_flush()
326 is_flushing = 0; in synth_flush()
338 return 0; in dt_sendchar()
343 int status = 0; in testkernel()
345 if (dt_getstatus() == 0xffff) { in testkernel()
352 else if (dt_stat & 0x8000) in testkernel()
353 return 0; in testkernel()
354 else if (dt_stat == 0x0dec) in testkernel()
355 pr_warn("dec_pc at 0x%x, software not loaded\n", in testkernel()
359 speakup_info.port_tts = 0; in testkernel()
384 speakup_info.flushing = 0; in do_catch_up()
399 ch = 0x0D; in do_catch_up()
411 in_escape = 0; in do_catch_up()
430 ch = 0; in do_catch_up()
452 int i = 0, failed = 0; in synth_probe()
455 for (i = 0; synth_portlist[i]; i++) { in synth_probe()
457 pr_warn("request_region: failed with 0x%x, %d\n", in synth_probe()
463 if (failed == 0) in synth_probe()
474 return 0; in synth_probe()
482 speakup_info.port_tts = 0; in dtpc_release()