Lines Matching refs:dst_hi
167 #define dst_hi dst[1] macro
262 emit_ia32_mov_r(dst_hi, src_hi, dstk, sstk, pprog); in emit_ia32_mov_r64()
265 emit_ia32_mov_i(dst_hi, 0, dstk, pprog); in emit_ia32_mov_r64()
277 emit_ia32_mov_i(dst_hi, hi, dstk, pprog); in emit_ia32_mov_i64()
323 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_le_r64()
329 STACK_VAR(dst_hi)); in emit_ia32_to_le_r64()
359 STACK_VAR(dst_hi)); in emit_ia32_to_le_r64()
371 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_be_r64()
377 STACK_VAR(dst_hi)); in emit_ia32_to_be_r64()
425 STACK_VAR(dst_hi)); in emit_ia32_to_be_r64()
585 emit_ia32_alu_r(is64, true, op, dst_hi, src_hi, dstk, sstk, in emit_ia32_alu_r64()
588 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in emit_ia32_alu_r64()
689 emit_ia32_alu_i(is64, true, op, dst_hi, hi, dstk, &prog); in emit_ia32_alu_i64()
691 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in emit_ia32_alu_i64()
702 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_neg64()
708 STACK_VAR(dst_hi)); in emit_ia32_neg64()
724 STACK_VAR(dst_hi)); in emit_ia32_neg64()
736 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_r64()
742 STACK_VAR(dst_hi)); in emit_ia32_lsh_r64()
776 STACK_VAR(dst_hi)); in emit_ia32_lsh_r64()
789 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_r64()
795 STACK_VAR(dst_hi)); in emit_ia32_arsh_r64()
829 STACK_VAR(dst_hi)); in emit_ia32_arsh_r64()
842 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_r64()
848 STACK_VAR(dst_hi)); in emit_ia32_rsh_r64()
882 STACK_VAR(dst_hi)); in emit_ia32_rsh_r64()
895 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_i64()
901 STACK_VAR(dst_hi)); in emit_ia32_lsh_i64()
931 STACK_VAR(dst_hi)); in emit_ia32_lsh_i64()
943 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_i64()
949 STACK_VAR(dst_hi)); in emit_ia32_rsh_i64()
980 STACK_VAR(dst_hi)); in emit_ia32_rsh_i64()
992 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_i64()
998 STACK_VAR(dst_hi)); in emit_ia32_arsh_i64()
1029 STACK_VAR(dst_hi)); in emit_ia32_arsh_i64()
1043 STACK_VAR(dst_hi)); in emit_ia32_mul_r64()
1046 EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX)); in emit_ia32_mul_r64()
1100 STACK_VAR(dst_hi)); in emit_ia32_mul_r64()
1105 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_r64()
1123 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi)); in emit_ia32_mul_i64()
1126 EMIT2(0xF7, add_1reg(0xE0, dst_hi)); in emit_ia32_mul_i64()
1160 STACK_VAR(dst_hi)); in emit_ia32_mul_i64()
1165 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_i64()
1500 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1570 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1591 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1614 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1632 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1669 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1703 emit_ia32_mov_i(dst_hi, hi, dstk, &prog); in do_jit()
1854 STACK_VAR(dst_hi)); in do_jit()
1859 add_2reg(0xC0, dst_hi, dst_hi)); in do_jit()
1870 STACK_VAR(dst_hi)); in do_jit()
1873 add_2reg(0xC0, dst_hi, IA32_EDX)); in do_jit()
1948 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
1959 STACK_VAR(dst_hi)); in do_jit()
1986 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
1996 STACK_VAR(dst_hi)); in do_jit()
2030 STACK_VAR(dst_hi)); in do_jit()
2037 add_2reg(0xC0, dreg_hi, dst_hi)); in do_jit()
2075 STACK_VAR(dst_hi)); in do_jit()
2082 add_2reg(0xC0, dreg_hi, dst_hi)); in do_jit()
2119 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2131 STACK_VAR(dst_hi)); in do_jit()
2166 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2177 STACK_VAR(dst_hi)); in do_jit()