35 /* mapping between fixed pmc index and intel_arch_events array */
45 		struct kvm_pmc *pmc;  in reprogram_fixed_counters()  local
47 		pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);  in reprogram_fixed_counters()
53 		reprogram_fixed_counter(pmc, new_ctrl, i);  in reprogram_fixed_counters()
101 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
102 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)  in intel_pmc_is_enabled()  argument
104 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);  in intel_pmc_is_enabled()
106 	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);  in intel_pmc_is_enabled()
196 	struct kvm_pmc *pmc;  in intel_msr_idx_to_pmc()  local
198 	pmc = get_fixed_pmc(pmu, msr);  in intel_msr_idx_to_pmc()
199 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);  in intel_msr_idx_to_pmc()
200 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);  in intel_msr_idx_to_pmc()
202 	return pmc;  in intel_msr_idx_to_pmc()
208 	struct kvm_pmc *pmc;  in intel_pmu_get_msr()  local
225 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_get_msr()
226 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_get_msr()
227 			u64 val = pmc_read_counter(pmc);  in intel_pmu_get_msr()
231 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_get_msr()
232 			u64 val = pmc_read_counter(pmc);  in intel_pmu_get_msr()
236 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_get_msr()
237 			msr_info->data = pmc->eventsel;  in intel_pmu_get_msr()
248 	struct kvm_pmc *pmc;  in intel_pmu_set_msr()  local
284 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_set_msr()
285 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_set_msr()
292 			pmc->counter += data - pmc_read_counter(pmc);  in intel_pmu_set_msr()
293 			if (pmc->perf_event)  in intel_pmu_set_msr()
294 				perf_event_period(pmc->perf_event,  in intel_pmu_set_msr()
295 						  get_sample_period(pmc, data));  in intel_pmu_set_msr()
297 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_set_msr()
298 			pmc->counter += data - pmc_read_counter(pmc);  in intel_pmu_set_msr()
299 			if (pmc->perf_event)  in intel_pmu_set_msr()
300 				perf_event_period(pmc->perf_event,  in intel_pmu_set_msr()
301 						  get_sample_period(pmc, data));  in intel_pmu_set_msr()
303 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_set_msr()
304 			if (data == pmc->eventsel)  in intel_pmu_set_msr()
307 				reprogram_gp_counter(pmc, data);  in intel_pmu_set_msr()
409 	struct kvm_pmc *pmc = NULL;  in intel_pmu_reset()  local
413 		pmc = &pmu->gp_counters[i];  in intel_pmu_reset()
415 		pmc_stop_counter(pmc);  in intel_pmu_reset()
416 		pmc->counter = pmc->eventsel = 0;  in intel_pmu_reset()
420 		pmc = &pmu->fixed_counters[i];  in intel_pmu_reset()
422 		pmc_stop_counter(pmc);  in intel_pmu_reset()
423 		pmc->counter = 0;  in intel_pmu_reset()