3  * KVM PMU support for Intel CPUs
19 #include "pmu.h"
38 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)  in reprogram_fixed_counters()  argument
42 	for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {  in reprogram_fixed_counters()
44 		u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);  in reprogram_fixed_counters()
47 		pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);  in reprogram_fixed_counters()
52 		__set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use);  in reprogram_fixed_counters()
56 	pmu->fixed_ctr_ctrl = data;  in reprogram_fixed_counters()
60 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)  in global_ctrl_changed()  argument
63 	u64 diff = pmu->global_ctrl ^ data;  in global_ctrl_changed()
65 	pmu->global_ctrl = data;  in global_ctrl_changed()
68 		reprogram_counter(pmu, bit);  in global_ctrl_changed()
71 static unsigned intel_find_arch_event(struct kvm_pmu *pmu,  in intel_find_arch_event()  argument
80 		    && (pmu->available_event_types & (1 << i)))  in intel_find_arch_event()
104 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);  in intel_pmc_is_enabled()  local
106 	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);  in intel_pmc_is_enabled()
109 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)  in intel_pmc_idx_to_pmc()  argument
112 		return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,  in intel_pmc_idx_to_pmc()
117 		return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);  in intel_pmc_idx_to_pmc()
124 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_is_valid_rdpmc_ecx()  local
129 	return (!fixed && idx >= pmu->nr_arch_gp_counters) ||  in intel_is_valid_rdpmc_ecx()
130 		(fixed && idx >= pmu->nr_arch_fixed_counters);  in intel_is_valid_rdpmc_ecx()
136 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_rdpmc_ecx_to_pmc()  local
143 		counters = pmu->fixed_counters;  in intel_rdpmc_ecx_to_pmc()
144 		num_counters = pmu->nr_arch_fixed_counters;  in intel_rdpmc_ecx_to_pmc()
146 		counters = pmu->gp_counters;  in intel_rdpmc_ecx_to_pmc()
147 		num_counters = pmu->nr_arch_gp_counters;  in intel_rdpmc_ecx_to_pmc()
151 	*mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];  in intel_rdpmc_ecx_to_pmc()
163 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)  in get_fw_gp_pmc()  argument
165 	if (!fw_writes_is_enabled(pmu_to_vcpu(pmu)))  in get_fw_gp_pmc()
168 	return get_gp_pmc(pmu, msr, MSR_IA32_PMC0);  in get_fw_gp_pmc()
173 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_is_valid_msr()  local
181 		ret = pmu->version > 1;  in intel_is_valid_msr()
184 		ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||  in intel_is_valid_msr()
185 			get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||  in intel_is_valid_msr()
186 			get_fixed_pmc(pmu, msr) || get_fw_gp_pmc(pmu, msr);  in intel_is_valid_msr()
195 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_msr_idx_to_pmc()  local
198 	pmc = get_fixed_pmc(pmu, msr);  in intel_msr_idx_to_pmc()
199 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);  in intel_msr_idx_to_pmc()
200 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);  in intel_msr_idx_to_pmc()
207 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_pmu_get_msr()  local
213 		msr_info->data = pmu->fixed_ctr_ctrl;  in intel_pmu_get_msr()
216 		msr_info->data = pmu->global_status;  in intel_pmu_get_msr()
219 		msr_info->data = pmu->global_ctrl;  in intel_pmu_get_msr()
222 		msr_info->data = pmu->global_ovf_ctrl;  in intel_pmu_get_msr()
225 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_get_msr()
226 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_get_msr()
229 				val & pmu->counter_bitmask[KVM_PMC_GP];  in intel_pmu_get_msr()
231 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_get_msr()
234 				val & pmu->counter_bitmask[KVM_PMC_FIXED];  in intel_pmu_get_msr()
236 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_get_msr()
247 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_pmu_set_msr()  local
254 		if (pmu->fixed_ctr_ctrl == data)  in intel_pmu_set_msr()
257 			reprogram_fixed_counters(pmu, data);  in intel_pmu_set_msr()
263 			pmu->global_status = data;  in intel_pmu_set_msr()
268 		if (pmu->global_ctrl == data)  in intel_pmu_set_msr()
270 		if (kvm_valid_perf_global_ctrl(pmu, data)) {  in intel_pmu_set_msr()
271 			global_ctrl_changed(pmu, data);  in intel_pmu_set_msr()
276 		if (!(data & pmu->global_ovf_ctrl_mask)) {  in intel_pmu_set_msr()
278 				pmu->global_status &= ~data;  in intel_pmu_set_msr()
279 			pmu->global_ovf_ctrl = data;  in intel_pmu_set_msr()
284 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_set_msr()
285 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_set_msr()
287 			    (data & ~pmu->counter_bitmask[KVM_PMC_GP]))  in intel_pmu_set_msr()
297 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_set_msr()
303 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_set_msr()
306 			if (!(data & pmu->reserved_bits)) {  in intel_pmu_set_msr()
318 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_pmu_refresh()  local
324 	pmu->nr_arch_gp_counters = 0;  in intel_pmu_refresh()
325 	pmu->nr_arch_fixed_counters = 0;  in intel_pmu_refresh()
326 	pmu->counter_bitmask[KVM_PMC_GP] = 0;  in intel_pmu_refresh()
327 	pmu->counter_bitmask[KVM_PMC_FIXED] = 0;  in intel_pmu_refresh()
328 	pmu->version = 0;  in intel_pmu_refresh()
329 	pmu->reserved_bits = 0xffffffff00200000ull;  in intel_pmu_refresh()
338 	pmu->version = eax.split.version_id;  in intel_pmu_refresh()
339 	if (!pmu->version)  in intel_pmu_refresh()
346 	pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,  in intel_pmu_refresh()
348 	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;  in intel_pmu_refresh()
349 	pmu->available_event_types = ~entry->ebx &  in intel_pmu_refresh()
352 	if (pmu->version == 1) {  in intel_pmu_refresh()
353 		pmu->nr_arch_fixed_counters = 0;  in intel_pmu_refresh()
355 		pmu->nr_arch_fixed_counters =  in intel_pmu_refresh()
358 		pmu->counter_bitmask[KVM_PMC_FIXED] =  in intel_pmu_refresh()
362 	pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |  in intel_pmu_refresh()
363 		(((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);  in intel_pmu_refresh()
364 	pmu->global_ctrl_mask = ~pmu->global_ctrl;  in intel_pmu_refresh()
365 	pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask  in intel_pmu_refresh()
369 		pmu->global_ovf_ctrl_mask &=  in intel_pmu_refresh()
376 		pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;  in intel_pmu_refresh()
378 	bitmap_set(pmu->all_valid_pmc_idx,  in intel_pmu_refresh()
379 		0, pmu->nr_arch_gp_counters);  in intel_pmu_refresh()
380 	bitmap_set(pmu->all_valid_pmc_idx,  in intel_pmu_refresh()
381 		INTEL_PMC_MAX_GENERIC, pmu->nr_arch_fixed_counters);  in intel_pmu_refresh()
389 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_pmu_init()  local
392 		pmu->gp_counters[i].type = KVM_PMC_GP;  in intel_pmu_init()
393 		pmu->gp_counters[i].vcpu = vcpu;  in intel_pmu_init()
394 		pmu->gp_counters[i].idx = i;  in intel_pmu_init()
395 		pmu->gp_counters[i].current_config = 0;  in intel_pmu_init()
399 		pmu->fixed_counters[i].type = KVM_PMC_FIXED;  in intel_pmu_init()
400 		pmu->fixed_counters[i].vcpu = vcpu;  in intel_pmu_init()
401 		pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;  in intel_pmu_init()
402 		pmu->fixed_counters[i].current_config = 0;  in intel_pmu_init()
408 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);  in intel_pmu_reset()  local
413 		pmc = &pmu->gp_counters[i];  in intel_pmu_reset()
420 		pmc = &pmu->fixed_counters[i];  in intel_pmu_reset()
426 	pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =  in intel_pmu_reset()
427 		pmu->global_ovf_ctrl = 0;  in intel_pmu_reset()