198 	vmcb->control.clean = 0;  in vmcb_mark_all_dirty()
203 	vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)  in vmcb_mark_all_clean()
209 	vmcb->control.clean &= ~(1 << bit);  in vmcb_mark_dirty()
225 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)  in vmcb_set_intercept()  argument
228 	__set_bit(bit, (unsigned long *)&control->intercepts);  in vmcb_set_intercept()
231 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)  in vmcb_clr_intercept()  argument
234 	__clear_bit(bit, (unsigned long *)&control->intercepts);  in vmcb_clr_intercept()
237 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)  in vmcb_is_intercept()  argument
240 	return test_bit(bit, (unsigned long *)&control->intercepts);  in vmcb_is_intercept()
247 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);  in set_dr_intercepts()
248 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);  in set_dr_intercepts()
249 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);  in set_dr_intercepts()
250 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);  in set_dr_intercepts()
251 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);  in set_dr_intercepts()
252 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);  in set_dr_intercepts()
253 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);  in set_dr_intercepts()
254 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);  in set_dr_intercepts()
255 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);  in set_dr_intercepts()
256 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);  in set_dr_intercepts()
257 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);  in set_dr_intercepts()
258 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);  in set_dr_intercepts()
259 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);  in set_dr_intercepts()
260 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);  in set_dr_intercepts()
261 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);  in set_dr_intercepts()
262 	vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);  in set_dr_intercepts()
271 	vmcb->control.intercepts[INTERCEPT_DR] = 0;  in clr_dr_intercepts()
281 	vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);  in set_exception_intercept()
291 	vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);  in clr_exception_intercept()
300 	vmcb_set_intercept(&vmcb->control, bit);  in svm_set_intercept()
309 	vmcb_clr_intercept(&vmcb->control, bit);  in svm_clr_intercept()
316 	return vmcb_is_intercept(&svm->vmcb->control, bit);  in svm_is_intercept()
321 	return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);  in vgif_enabled()
327 		svm->vmcb->control.int_ctl |= V_GIF_MASK;  in enable_gif()
335 		svm->vmcb->control.int_ctl &= ~V_GIF_MASK;  in disable_gif()
343 		return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);  in gif_set()
431 	svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;  in avic_update_vapic_bar()