32 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
41  * TSC can be unstable due to cpufreq or due to unsynced TSCs
227 	 * Fall back to jiffies if there's no TSC available:  in native_sched_clock()
228 	 * ( But note that we still use it if the TSC is marked  in native_sched_clock()
240  * Generate a sched_clock if you already have a TSC value.
242 u64 native_sched_clock_from_tsc(u64 tsc)  in native_sched_clock_from_tsc()  argument
244 	return cycles_2_ns(tsc);  in native_sched_clock_from_tsc()
280  * disable flag for tsc. Takes effect by clearing the TSC cpu flag
308 __setup("tsc=", tsc_setup);
314  * Read TSC and the reference counters. Take care of any disturbances
336  * Calculate the TSC frequency from HPET reference
353  * Calculate the TSC frequency from PMTimer reference
382  * Try to calibrate the TSC against the Programmable
383  * Interrupt Timer and return the frequency of the TSC
390 	u64 tsc, t1, t2, delta;  in pit_calibrate_tsc()  local
420 	tsc = t1 = t2 = get_cycles();  in pit_calibrate_tsc()
427 		delta = t2 - tsc;  in pit_calibrate_tsc()
428 		tsc = t2;  in pit_calibrate_tsc()
470  *    see the same MSB (and overhead like doing a single TSC
486  * use the TSC value at the transitions to calculate a pretty
487  * good value for the TSC frequency.
499 	u64 tsc = 0, prev_tsc = 0;  in pit_expect_msb()  local
504 		prev_tsc = tsc;  in pit_expect_msb()
505 		tsc = get_cycles();  in pit_expect_msb()
508 	*tscp = tsc;  in pit_expect_msb()
512 	 * will be based on the error terms on the TSC values.  in pit_expect_msb()
529 	u64 tsc, delta;  in quick_pit_calibrate()  local
561 	if (pit_expect_msb(0xff, &tsc, &d1)) {  in quick_pit_calibrate()
566 			delta -= tsc;  in quick_pit_calibrate()
584 			 * all TSC reads were stable wrt the PIT.  in quick_pit_calibrate()
594 	pr_info("Fast TSC calibration failed\n");  in quick_pit_calibrate()
604 	 * any odd delays anywhere, and the TSC reads are  in quick_pit_calibrate()
613 	pr_info("Fast TSC calibration using PIT\n");  in quick_pit_calibrate()
619  * Determine TSC frequency via CPUID, else return 0.
634 	/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */  in native_calibrate_tsc()
652 	 * TSC frequency reported directly by CPUID is a "hardware reported"  in native_calibrate_tsc()
676 	 * For Atom SoCs TSC is the only reliable clocksource.  in native_calibrate_tsc()
677 	 * Mark TSC reliable so no watchdog on it.  in native_calibrate_tsc()
731 	 * zero. In each wait loop iteration we read the TSC and check  in pit_hpet_ptimer_calibrate_cpu()
741 	 * We use separate TSC readouts and check inside of the  in pit_hpet_ptimer_calibrate_cpu()
768 		/* Pick the lowest PIT TSC calibration so far */  in pit_hpet_ptimer_calibrate_cpu()
823 		/* We don't have an alternative source, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
829 		/* The alternative source failed as well, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
929  * Even on processors with invariant TSC, TSC gets reset in some the
930  * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
968  * Frequency scaling support. Adjust the TSC based timer when the CPU frequency
971  * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC
1037  * If ART is present detect the numerator:denominator to convert to TSC
1047 	 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,  in detect_art()
1048 	 * and the TSC counter resets must not occur asynchronously.  in detect_art()
1077  * We used to compare the TSC to the cycle_last value in the clocksource
1080  * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1081  * is smaller than the cycle_last reference value due to a TSC which
1106 	pr_info("Marking TSC unstable due to clocksource watchdog\n");  in tsc_cs_mark_unstable()
1128 	.name			= "tsc-early",
1144  * this one will immediately take over. We will only register if TSC has
1148 	.name			= "tsc",
1172 	pr_info("Marking TSC unstable due to %s\n", reason);  in mark_tsc_unstable()
1189 		/* Geode_LX - the OLPC CPU has a very reliable TSC */  in check_system_tsc_reliable()
1199  * Make an educated guess if the TSC is trustworthy and synchronized
1219 	 * Exceptions must mark TSC as unstable:  in unsynchronized_tsc()
1231  * Convert ART to TSC given numerator/denominator found in detect_art()
1251  * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1256  * to TSC.
1260  * that this flag is set before conversion to TSC is attempted.
1292  * tsc_refine_calibration_work - Further refine tsc freq calibration
1296  * second to further refine the TSC freq value. Since this is
1313 	/* Don't bother refining TSC on unstable systems */  in tsc_refine_calibration_work()
1356 	pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",  in tsc_refine_calibration_work()
1360 	/* Inform the TSC deadline clockevent devices about the recalibration */  in tsc_refine_calibration_work()
1394 	 * When TSC frequency is known (retrieved via MSR or CPUID), we skip  in init_tsc_clocksource()
1417 	/* Make sure that cpu and tsc are not already calibrated */  in determine_cpu_tsc_frequencies()
1450 		pr_info("Detected %lu.%03lu MHz TSC",  in determine_cpu_tsc_frequencies()
1467 	/* Sanitize TSC ADJUST before cyc2ns gets initialized */  in tsc_enable_sched_clock()
1477 	/* Don't change UV TSC multi-chassis synchronization */  in tsc_early_init()
1504 			mark_tsc_unstable("could not calculate TSC khz");  in tsc_init()
1535  * If we have a constant TSC and are using the TSC for the delay loop,