1 // SPDX-License-Identifier: GPL-2.0-only
28 #include <asm/intel-family.h>
38 #define KHZ	1000
79 		data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);  in cyc2ns_read_begin()
80 		data->cyc2ns_mul    = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);  in cyc2ns_read_begin()
81 		data->cyc2ns_shift  = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);  in cyc2ns_read_begin()
106  *  cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
107  *  (64-bit result) can be used.
112  *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
149 	 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit  in __set_cyc2ns_scale()
150 	 * value) - refer perf_event_mmap_page documentation in perf_event.h.  in __set_cyc2ns_scale()
157 	data.cyc2ns_offset = ns_now -  in __set_cyc2ns_scale()
162 	raw_write_seqcount_latch(&c2n->seq);  in __set_cyc2ns_scale()
163 	c2n->data[0] = data;  in __set_cyc2ns_scale()
164 	raw_write_seqcount_latch(&c2n->seq);  in __set_cyc2ns_scale()
165 	c2n->data[1] = data;  in __set_cyc2ns_scale()
189 	seqcount_latch_init(&c2n->seq);  in cyc2ns_init_boot_cpu()
202 	struct cyc2ns_data *data = c2n->data;  in cyc2ns_init_secondary_cpus()
206 			seqcount_latch_init(&c2n->seq);  in cyc2ns_init_secondary_cpus()
208 			c2n->data[0] = data[0];  in cyc2ns_init_secondary_cpus()
209 			c2n->data[1] = data[1];  in cyc2ns_init_secondary_cpus()
215  * Scheduler clock - returns current time in nanosec units.
236 	return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);  in native_sched_clock()
329 		if ((t2 - t1) < thresh)  in tsc_read_refs()
344 	hpet2 -= hpet1;  in calc_hpet_ref()
364 	pm2 -= pm1;  in calc_pmtimer_ref()
373 #define CAL_LATCH	(PIT_TICK_RATE / (1000 / CAL_MS))
374 #define CAL_PIT_LOOPS	1000
377 #define CAL2_LATCH	(PIT_TICK_RATE / (1000 / CAL2_MS))
427 		delta = t2 - tsc;  in pit_calibrate_tsc()
449 	delta = t2 - t1;  in pit_calibrate_tsc()
457  * non-virtualized hardware.
461  *  - the PIT is running at roughly 1.19MHz
463  *  - each IO is going to take about 1us on real hardware,
466  *    update - anything else implies a unacceptably slow CPU
469  *  - with 256 PIT ticks to read the value, we have 214us to
473  *  - We're doing 2 reads per loop (LSB, MSB), and we expect
478  *  - if the PIT is stuck, and we see *many* more reads, we
507 	*deltap = get_cycles() - prev_tsc;  in pit_expect_msb()
524 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
539 	 * Counter 2, mode 0 (one-shot), binary count  in quick_pit_calibrate()
543 	 * final output frequency as a decrement-by-one),  in quick_pit_calibrate()
556 	 * to do that is to just read back the 16-bit counter  in quick_pit_calibrate()
563 			if (!pit_expect_msb(0xff-i, &delta, &d2))  in quick_pit_calibrate()
566 			delta -= tsc;  in quick_pit_calibrate()
589 			if (!pit_verify_msb(0xfe - i))  in quick_pit_calibrate()
607 	 * kHz = ticks / time-in-seconds / 1000;  in quick_pit_calibrate()
608 	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000  in quick_pit_calibrate()
609 	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)  in quick_pit_calibrate()
612 	do_div(delta, i*256*1000);  in quick_pit_calibrate()
640 	crystal_khz = ecx_hz / 1000;  in native_calibrate_tsc()
665 		unsigned int eax_base_mhz, ebx, ecx, edx;  in native_calibrate_tsc()  local
667 		cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);  in native_calibrate_tsc()
668 		crystal_khz = eax_base_mhz * 1000 *  in native_calibrate_tsc()
689 	lapic_timer_period = crystal_khz * 1000 / HZ;  in native_calibrate_tsc()
709 	return eax_base_mhz * 1000;  in cpu_khz_from_cpuid()
779 		tsc2 = (tsc2 - tsc1) * 1000000LL;  in pit_hpet_ptimer_calibrate_cpu()
866  * native_calibrate_cpu_early - can calibrate the cpu early in boot
884  * native_calibrate_cpu - calibrate the cpu
908 	else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)  in recalibrate_cpu_khz()
956 	offset = cyc2ns_suspend - sched_clock();  in tsc_restore_sched_clock_state()
993 		ref_freq = freq->old;  in time_cpufreq_notifier()
998 	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||  in time_cpufreq_notifier()
999 	    (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {  in time_cpufreq_notifier()
1001 			cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);  in time_cpufreq_notifier()
1003 		tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);  in time_cpufreq_notifier()
1004 		if (!(freq->flags & CPUFREQ_CONST_LOOPS))  in time_cpufreq_notifier()
1007 		set_cyc2ns_scale(tsc_khz, freq->policy->cpu, rdtsc());  in time_cpufreq_notifier()
1047 	 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,  in detect_art()
1078  * structure to avoid a nasty time-warp. This can be observed in a
1089  * checking the result of read_tsc() - cycle_last for being negative.
1128 	.name			= "tsc-early",
1189 		/* Geode_LX - the OLPC CPU has a very reliable TSC */  in check_system_tsc_reliable()
1251  * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
1255  * software requests a cross-timestamp, this function converts system timestamp
1263  * struct system_counterval_t - system counter value with the pointer to the
1292  * tsc_refine_calibration_work - Further refine tsc freq calibration
1293  * @work - ignored.
1344 	delta = tsc_stop - tsc_start;  in tsc_refine_calibration_work()
1352 	if (abs(tsc_khz - freq) > tsc_khz/100)  in tsc_refine_calibration_work()
1357 		(unsigned long)tsc_khz / 1000,  in tsc_refine_calibration_work()
1358 		(unsigned long)tsc_khz % 1000);  in tsc_refine_calibration_work()
1427 		/* We should not be here with non-native cpu calibration */  in determine_cpu_tsc_frequencies()
1433 	 * Trust non-zero tsc_khz as authoritative,  in determine_cpu_tsc_frequencies()
1439 	else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)  in determine_cpu_tsc_frequencies()
1477 	/* Don't change UV TSC multi-chassis synchronization */  in tsc_early_init()
1538  * cpus in the socket - this should be a safe assumption.