466 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)  in amd_set_core_ssb_state()  argument
472 		msr |= ssbd_tif_to_amd_ls_cfg(tifn);  in amd_set_core_ssb_state()
477 	if (tifn & _TIF_SSBD) {  in amd_set_core_ssb_state()
505 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)  in amd_set_core_ssb_state()  argument
507 	u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);  in amd_set_core_ssb_state()
513 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)  in amd_set_ssb_virt_state()  argument
519 	wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));  in amd_set_ssb_virt_state()
529 						      unsigned long tifn)  in __speculation_ctrl_update()  argument
531 	unsigned long tif_diff = tifp ^ tifn;  in __speculation_ctrl_update()
540 			amd_set_ssb_virt_state(tifn);  in __speculation_ctrl_update()
543 			amd_set_core_ssb_state(tifn);  in __speculation_ctrl_update()
547 		msr |= ssbd_tif_to_spec_ctrl(tifn);  in __speculation_ctrl_update()
554 		msr |= stibp_tif_to_spec_ctrl(tifn);  in __speculation_ctrl_update()
609 	unsigned long tifp, tifn;  in __switch_to_xtra()  local
611 	tifn = READ_ONCE(task_thread_info(next_p)->flags);  in __switch_to_xtra()
618 	if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&  in __switch_to_xtra()
624 		msk = tifn & _TIF_BLOCKSTEP;  in __switch_to_xtra()
629 	if ((tifp ^ tifn) & _TIF_NOTSC)  in __switch_to_xtra()
632 	if ((tifp ^ tifn) & _TIF_NOCPUID)  in __switch_to_xtra()
633 		set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));  in __switch_to_xtra()
635 	if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {  in __switch_to_xtra()
636 		__speculation_ctrl_update(tifp, tifn);  in __switch_to_xtra()
639 		tifn = speculation_ctrl_update_tif(next_p);  in __switch_to_xtra()
642 		__speculation_ctrl_update(~tifn, tifn);  in __switch_to_xtra()
645 	if ((tifp ^ tifn) & _TIF_SLD)  in __switch_to_xtra()
646 		switch_to_sld(tifn);  in __switch_to_xtra()