Lines Matching +full:deep +full:- +full:touch
1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
54 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * Processors which have self-snooping capability can handle conflicting
69 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
103 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
170 if (c->x86 != 6) in bad_spectre_microcode()
174 if (c->x86_model == spectre_bad_microcodes[i].model && in bad_spectre_microcode()
175 c->x86_stepping == spectre_bad_microcodes[i].stepping) in bad_spectre_microcode()
176 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
186 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
189 c->cpuid_level = cpuid_eax(0); in early_init_intel()
194 if ((c->x86 == 0xf && c->x86_model >= 0x03) || in early_init_intel()
195 (c->x86 == 0x6 && c->x86_model >= 0x0e)) in early_init_intel()
198 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
199 c->microcode = intel_get_microcode_revision(); in early_init_intel()
225 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && in early_init_intel()
226 c->microcode < 0x20e) { in early_init_intel()
235 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
236 c->x86_cache_alignment = 128; in early_init_intel()
240 if (c->x86 == 0xF && c->x86_model == 0x3 in early_init_intel()
241 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
242 c->x86_phys_bits = 36; in early_init_intel()
245 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
246 * with P/T states and does not stop in deep C-states. in early_init_intel()
249 * cabinets - we turn it off in that case explicitly.) in early_init_intel()
251 if (c->x86_power & (1 << 8)) { in early_init_intel()
257 if (c->x86 == 6) { in early_init_intel()
258 switch (c->x86_model) { in early_init_intel()
280 if (c->x86 == 6 && c->x86_model < 15) in early_init_intel()
287 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
306 if (c->x86 == 5 && c->x86_model == 9) { in early_init_intel()
311 if (c->cpuid_level >= 0x00000001) { in early_init_intel()
321 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); in early_init_intel()
362 if (!c->cpu_index) in intel_smp_check()
368 if (c->x86 == 5 && in intel_smp_check()
369 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
370 c->x86_model <= 3) { in intel_smp_check()
397 if (c->x86 == 5 && c->x86_model < 9) { in intel_workarounds()
402 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); in intel_workarounds()
412 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
430 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { in intel_workarounds()
444 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
445 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
453 switch (c->x86) { in intel_workarounds()
458 case 6: /* PII/PIII only like movsl with 8-byte alignment */ in intel_workarounds()
461 case 15: /* P4 is OK down to 8-byte alignment */ in intel_workarounds()
556 nr_keyids = (1UL << keyid_bits) - 1; in detect_tme()
573 c->x86_phys_bits -= keyid_bits; in detect_tme()
632 if (c->cpuid_level > 9) { in init_intel()
652 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && in init_intel()
653 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) in init_intel()
656 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && in init_intel()
657 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) in init_intel()
661 if (c->x86 == 15) in init_intel()
662 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
663 if (c->x86 == 6) in init_intel()
671 if (c->x86 == 6) { in init_intel()
672 unsigned int l2 = c->x86_cache_size; in init_intel()
675 switch (c->x86_model) { in init_intel()
686 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
687 p = "Celeron-A"; in init_intel()
697 strcpy(c->x86_model_id, p); in init_intel()
700 if (c->x86 == 15) in init_intel()
702 if (c->x86 == 6) in init_intel()
733 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) in intel_size_cache()
737 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
740 if ((c->x86 == 5) && (c->x86_model == 9)) in intel_size_cache()
768 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
770 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
771 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
772 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
773 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
775 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
776 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
777 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
778 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
779 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
780 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
782 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
787 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
788 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
789 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
791 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
792 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
793 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
794 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
795 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
796 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
797 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
798 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
799 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
800 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
801 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
802 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
803 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
900 if (c->cpuid_level < 2) in intel_detect_tlb()
927 [0] = "486 DX-25/33",
928 [1] = "486 DX-50",
933 [7] = "486 DX/2-WB",
935 [9] = "486 DX/4-WB"
940 [0] = "Pentium 60/66 A-step",
942 [2] = "Pentium 75 - 200",
945 [7] = "Mobile Pentium 75 - 200",
952 [0] = "Pentium Pro A-step",
1047 pr_info("warning about user-space split_locks\n"); in split_lock_setup()
1050 pr_info("sending SIGBUS on user-space split_locks\n"); in split_lock_setup()
1089 current->comm, current->pid, ip); in split_lock_warn()
1093 * progress and set TIF_SLD so the detection is re-enabled via in split_lock_warn()
1108 current->comm, current->pid, in handle_guest_split_lock()
1111 current->thread.error_code = 0; in handle_guest_split_lock()
1112 current->thread.trap_nr = X86_TRAP_AC; in handle_guest_split_lock()
1120 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal) in handle_user_split_lock()
1122 split_lock_warn(regs->ip); in handle_user_split_lock()
1128 * different split-lock detection modes. It sets the MSR for the
1145 * - 0: CPU models that are known to have the per-core split-lock detection
1148 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1149 * bit 5 to enumerate the per-core split-lock detection feature.
1177 switch (m->driver_data) { in cpu_set_core_cap_bits()