1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/spec-ctrl.h>
19 #include <asm/pci-direct.h>
38  * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
82  *	and	section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
108 #define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */  in init_amd_k5()
111 	if (c->x86_model == 9 || c->x86_model == 10) {  in init_amd_k5()
122 	int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);  in init_amd_k6()
124 	if (c->x86_model < 6) {  in init_amd_k6()
125 		/* Based on AMD doc 20734R - June 2000 */  in init_amd_k6()
126 		if (c->x86_model == 0) {  in init_amd_k6()
133 	if (c->x86_model == 6 && c->x86_stepping == 1) {  in init_amd_k6()
139 		pr_info("AMD K6 stepping B detected - ");  in init_amd_k6()
150 		while (n--)  in init_amd_k6()
153 		d = d2-d;  in init_amd_k6()
162 	if (c->x86_model < 8 ||  in init_amd_k6()
163 	   (c->x86_model == 8 && c->x86_stepping < 8)) {  in init_amd_k6()
182 	if ((c->x86_model == 8 && c->x86_stepping > 7) ||  in init_amd_k6()
183 	     c->x86_model == 9 || c->x86_model == 13) {  in init_amd_k6()
204 	if (c->x86_model == 10) {  in init_amd_k6()
222 	if (c->x86_model >= 6 && c->x86_model <= 10) {  in init_amd_k7()
235 	if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {  in init_amd_k7()
245 	if (!c->cpu_index)  in init_amd_k7()
253 	if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||  in init_amd_k7()
254 	    (c->x86_stepping == 1)))  in init_amd_k7()
258 	if ((c->x86_model == 7) && (c->x86_stepping == 0))  in init_amd_k7()
265 	 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for  in init_amd_k7()
268 	if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||  in init_amd_k7()
269 	    ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||  in init_amd_k7()
270 	     (c->x86_model > 7))  in init_amd_k7()
277 	 * Don't taint if we are running SMP kernel on a single non-MP  in init_amd_k7()
295 	for (i = apicid - 1; i >= 0; i--) {  in nearby_node()
310  * Fix up cpu_core_id for pre-F17h systems to be in the
311  * [0 .. cores_per_node - 1] range. Not really needed but
318 	if (c->x86 >= 0x17)  in legacy_fixup_core_id()
321 	cus_per_node = c->x86_max_cores / nodes_per_socket;  in legacy_fixup_core_id()
322 	c->cpu_core_id %= cus_per_node;  in legacy_fixup_core_id()
327  * (1) AMD multi-node processors
336 	/* get information required for multi-node processors */  in amd_get_topology()
345 		if (c->x86 == 0x15)  in amd_get_topology()
346 			c->cu_id = ebx & 0xff;  in amd_get_topology()
348 		if (c->x86 >= 0x17) {  in amd_get_topology()
349 			c->cpu_core_id = ebx & 0xff;  in amd_get_topology()
352 				c->x86_max_cores /= smp_num_siblings;  in amd_get_topology()
361 			c->x86_coreid_bits = get_count_order(c->x86_max_cores);  in amd_get_topology()
390 	bits = c->x86_coreid_bits;  in amd_detect_cmp()
392 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);  in amd_detect_cmp()
394 	c->phys_proc_id = c->initial_apicid >> bits;  in amd_detect_cmp()
396 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;  in amd_detect_cmp()
445 	unsigned apicid = c->apicid;  in srat_detect_node()
452 	 * On multi-fabric platform (e.g. Numascale NumaChip) a  in srat_detect_node()
453 	 * platform-specific handler needs to be called to fixup some  in srat_detect_node()
463 		 * - The CPU is missing memory and no node was created.  In  in srat_detect_node()
466 		 * - The APIC IDs differ from the HyperTransport node IDs  in srat_detect_node()
479 		int ht_nodeid = c->initial_apicid;  in srat_detect_node()
497 	if (c->extended_cpuid_level < 0x80000008)  in early_init_amd_mc()
502 	c->x86_max_cores = (ecx & 0xff) + 1;  in early_init_amd_mc()
509 		while ((1 << bits) < c->x86_max_cores)  in early_init_amd_mc()
513 	c->x86_coreid_bits = bits;  in early_init_amd_mc()
521 	if (c->x86 >= 0xf) {  in bsp_init_amd()
541 		if (c->x86 > 0x10 ||  in bsp_init_amd()
542 		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {  in bsp_init_amd()
551 	if (c->x86 == 0x15) {  in bsp_init_amd()
553 		u32 cpuid, assoc;  in bsp_init_amd()  local
556 		assoc	 = cpuid >> 16 & 0xff;  in bsp_init_amd()
557 		upperbit = ((cpuid >> 24) << 10) / assoc;  in bsp_init_amd()
559 		va_align.mask	  = (upperbit - 1) & PAGE_MASK;  in bsp_init_amd()
583 	    c->x86 >= 0x15 && c->x86 <= 0x17) {  in bsp_init_amd()
586 		switch (c->x86) {  in bsp_init_amd()
630 		 * will be a value above 32-bits this is still done for  in early_detect_mem_encrypt()
633 		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;  in early_detect_mem_encrypt()
660 	if (c->x86 == 6)  in early_init_amd()
664 	if (c->x86 >= 0xf)  in early_init_amd()
667 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);  in early_init_amd()
670 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_amd()
671 	 * with P/T states and does not stop in deep C-states  in early_init_amd()
673 	if (c->x86_power & (1 << 8)) {  in early_init_amd()
679 	if (c->x86_power & BIT(12))  in early_init_amd()
686 	if (c->x86 == 5)  in early_init_amd()
687 		if (c->x86_model == 13 || c->x86_model == 9 ||  in early_init_amd()
688 		    (c->x86_model == 8 && c->x86_stepping >= 8))  in early_init_amd()
693 	 * ApicID can always be treated as an 8-bit value for AMD APIC versions  in early_init_amd()
699 		if (c->x86 > 0x16)  in early_init_amd()
701 		else if (c->x86 >= 0xf) {  in early_init_amd()
719 	/* F16h erratum 793, CVE-2013-6885 */  in early_init_amd()
720 	if (c->x86 == 0x16 && c->x86_model <= 0xf)  in early_init_amd()
725 	 * used to select the proper idle routine and to enable the check  in early_init_amd()
734 	/* Re-enable TopologyExtensions if switched off by BIOS */  in early_init_amd()
735 	if (c->x86 == 0x15 &&  in early_init_amd()
736 	    (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&  in early_init_amd()
743 				pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");  in early_init_amd()
767 	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {  in init_amd_k8()
775 	if (!c->x86_model_id[0])  in init_amd_k8()
776 		strcpy(c->x86_model_id, "Hammer");  in init_amd_k8()
783 	 * Errata 63 for SH-B3 steppings  in init_amd_k8()
814 	 * degradation for certain nested-paging guests. Prevent this conversion  in init_amd_gh()
842 		return -EINVAL;  in rdrand_cmdline()
847 		return -EINVAL;  in rdrand_cmdline()
903 	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {  in init_amd_bd()
944 	if (c->x86 >= 0x10)  in init_amd()
948 	c->apicid = hard_smp_processor_id();  in init_amd()
951 	if (c->x86 < 6)  in init_amd()
954 	switch (c->x86) {  in init_amd()
971 	if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))  in init_amd()
1001 	if (c->x86 > 0x11)  in init_amd()
1027 	if (c->x86 == 6) {  in amd_size_cache()
1029 		if (c->x86_model == 3 && c->x86_stepping == 0)  in amd_size_cache()
1032 		if (c->x86_model == 4 &&  in amd_size_cache()
1033 			(c->x86_stepping == 0 || c->x86_stepping == 1))  in amd_size_cache()
1045 	if (c->x86 < 0xf)  in cpu_detect_tlb_amd()
1048 	if (c->extended_cpuid_level < 0x80000006)  in cpu_detect_tlb_amd()
1060 	if (c->x86 == 0xf) {  in cpu_detect_tlb_amd()
1077 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {  in cpu_detect_tlb_amd()
1097 			  [7] = "486 DX/2-WB",
1099 			  [9] = "486 DX/4-WB",
1100 			  [14] = "Am5x86-WT",
1101 			  [15] = "Am5x86-WB"
1122  * variable number of family-specific model-stepping ranges created by
1133 #define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
1172 	/* OSVW unavailable or ID unknown, match family-model-stepping range */  in cpu_has_amd_erratum()
1173 	ms = (cpu->x86_model << 4) | cpu->x86_stepping;  in cpu_has_amd_erratum()
1175 		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&  in cpu_has_amd_erratum()
1195 		wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);  in set_dr_addr_mask()