18 #define PCI_DEVICE_ID_AMD_17H_ROOT	0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT	0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT	0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT	0x1630
22 #define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464
23 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
24 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
25 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
26 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
27 #define PCI_DEVICE_ID_AMD_19H_DF_F4	0x1654
42 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
95 	{ 0x00, 0x18, 0x20 },
96 	{ 0xff, 0x00, 0x20 },
97 	{ 0xfe, 0x00, 0x20 },
146 	err = pci_write_config_dword(root, 0x60, address);  in __amd_smn_rw()
148 		pr_warn("Error programming SMN address 0x%x.\n", address);  in __amd_smn_rw()
152 	err = (write ? pci_write_config_dword(root, 0x64, *value)  in __amd_smn_rw()
153 		     : pci_read_config_dword(root, 0x64, value));  in __amd_smn_rw()
155 		pr_warn("Error %s SMN address 0x%x.\n",  in __amd_smn_rw()
201 	ficaa |= reg & 0x3FC;  in amd_df_indirect_read()
202 	ficaa |= (func & 0x7) << 11;  in amd_df_indirect_read()
207 	err = pci_write_config_dword(F4, 0x5C, ficaa);  in amd_df_indirect_read()
209 		pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);  in amd_df_indirect_read()
213 	err = pci_read_config_dword(F4, 0x98, lo);  in amd_df_indirect_read()
215 		pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);  in amd_df_indirect_read()
232 	u16 roots_per_misc = 0;  in amd_cache_northbridges()
233 	u16 misc_count = 0;  in amd_cache_northbridges()
234 	u16 root_count = 0;  in amd_cache_northbridges()
238 		return 0;  in amd_cache_northbridges()
278 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_cache_northbridges()
305 	if (!cpuid_edx(0x80000006))  in amd_cache_northbridges()
306 		return 0;  in amd_cache_northbridges()
310 	 * limitations because of E382 and E388 on family 0x10.  in amd_cache_northbridges()
312 	if (boot_cpu_data.x86 == 0x10 &&  in amd_cache_northbridges()
313 	    boot_cpu_data.x86_model >= 0x8 &&  in amd_cache_northbridges()
314 	    (boot_cpu_data.x86_model > 0x9 ||  in amd_cache_northbridges()
315 	     boot_cpu_data.x86_stepping >= 0x1))  in amd_cache_northbridges()
318 	if (boot_cpu_data.x86 == 0x15)  in amd_cache_northbridges()
321 	/* L3 cache partitioning is supported on family 0x15 */  in amd_cache_northbridges()
322 	if (boot_cpu_data.x86 == 0x15)  in amd_cache_northbridges()
325 	return 0;  in amd_cache_northbridges()
337 	u32 vendor = device & 0xffff;  in early_is_amd_nb()
364 	if (boot_cpu_data.x86 < 0x10)  in amd_get_mmconfig_range()
391 		return 0;  in amd_get_subcaches()
393 	pci_read_config_dword(link, 0x1d4, &mask);  in amd_get_subcaches()
395 	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;  in amd_get_subcaches()
405 	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)  in amd_set_subcaches()
409 	if (reset == 0) {  in amd_set_subcaches()
410 		pci_read_config_dword(nb->link, 0x1d4, &reset);  in amd_set_subcaches()
411 		pci_read_config_dword(nb->misc, 0x1b8, &ban);  in amd_set_subcaches()
412 		ban &= 0x180000;  in amd_set_subcaches()
416 	if (mask != 0xf) {  in amd_set_subcaches()
417 		pci_read_config_dword(nb->misc, 0x1b8, &reg);  in amd_set_subcaches()
418 		pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);  in amd_set_subcaches()
423 	mask |= (0xf ^ (1 << cuid)) << 26;  in amd_set_subcaches()
425 	pci_write_config_dword(nb->link, 0x1d4, mask);  in amd_set_subcaches()
428 	pci_read_config_dword(nb->link, 0x1d4, &reg);  in amd_set_subcaches()
430 		pci_read_config_dword(nb->misc, 0x1b8, &reg);  in amd_set_subcaches()
431 		reg &= ~0x180000;  in amd_set_subcaches()
432 		pci_write_config_dword(nb->misc, 0x1b8, reg | ban);  in amd_set_subcaches()
435 	return 0;  in amd_set_subcaches()
452 	for (i = 0; i != amd_northbridges.num; i++)  in amd_cache_gart()
453 		pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);  in amd_cache_gart()
472 	flushed = 0;  in amd_flush_garts()
473 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_flush_garts()
474 		pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,  in amd_flush_garts()
478 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_flush_garts()
483 					      0x9c, &w);  in amd_flush_garts()
497 #define MSR_AMD64_IC_CFG 0xC0011021  in __fix_erratum_688()
509 	if (boot_cpu_data.x86 != 0x14)  in fix_erratum_688()
515 	F4 = node_to_amd_nb(0)->link;  in fix_erratum_688()
519 	if (pci_read_config_dword(F4, 0x164, &val))  in fix_erratum_688()
525 	on_each_cpu(__fix_erratum_688, NULL, 0);  in fix_erratum_688()
537 	return 0;  in init_amd_nbs()