Lines Matching refs:C
435 [ C(L1D ) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
438 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
442 [ C(RESULT_MISS) ] = 0x0,
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
449 [ C(L1I ) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x0,
452 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = 0x0,
460 [ C(RESULT_MISS) ] = 0x0,
463 [ C(LL ) ] = {
464 [ C(OP_READ) ] = {
465 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
466 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
470 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
472 [ C(OP_PREFETCH) ] = {
473 [ C(RESULT_ACCESS) ] = 0x0,
474 [ C(RESULT_MISS) ] = 0x0,
477 [ C(DTLB) ] = {
478 [ C(OP_READ) ] = {
479 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
480 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
482 [ C(OP_WRITE) ] = {
483 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
484 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
486 [ C(OP_PREFETCH) ] = {
487 [ C(RESULT_ACCESS) ] = 0x0,
488 [ C(RESULT_MISS) ] = 0x0,
491 [ C(ITLB) ] = {
492 [ C(OP_READ) ] = {
493 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
494 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
496 [ C(OP_WRITE) ] = {
497 [ C(RESULT_ACCESS) ] = -1,
498 [ C(RESULT_MISS) ] = -1,
500 [ C(OP_PREFETCH) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
505 [ C(BPU ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
508 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = -1,
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = -1,
516 [ C(RESULT_MISS) ] = -1,
519 [ C(NODE) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
522 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
526 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0x0,
530 [ C(RESULT_MISS) ] = 0x0,
540 [ C(LL ) ] = {
541 [ C(OP_READ) ] = {
542 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
544 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
548 [ C(OP_WRITE) ] = {
549 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
551 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
555 [ C(OP_PREFETCH) ] = {
556 [ C(RESULT_ACCESS) ] = 0x0,
557 [ C(RESULT_MISS) ] = 0x0,
560 [ C(NODE) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
564 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
570 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
573 [ C(OP_PREFETCH) ] = {
574 [ C(RESULT_ACCESS) ] = 0x0,
575 [ C(RESULT_MISS) ] = 0x0,
628 [ C(LL ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
631 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
635 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
639 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
644 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
645 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
647 [ C(OP_WRITE) ] = {
648 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
649 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
651 [ C(OP_PREFETCH) ] = {
652 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
653 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
663 [ C(L1D) ] = {
664 [ C(OP_READ) ] = {
665 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
666 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
668 [ C(OP_WRITE) ] = {
669 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
670 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
672 [ C(OP_PREFETCH) ] = {
673 [ C(RESULT_ACCESS) ] = 0x0,
674 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
677 [ C(L1I ) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x0,
680 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
686 [ C(OP_PREFETCH) ] = {
687 [ C(RESULT_ACCESS) ] = 0x0,
688 [ C(RESULT_MISS) ] = 0x0,
691 [ C(LL ) ] = {
692 [ C(OP_READ) ] = {
694 [ C(RESULT_ACCESS) ] = 0x01b7,
696 [ C(RESULT_MISS) ] = 0x01b7,
698 [ C(OP_WRITE) ] = {
700 [ C(RESULT_ACCESS) ] = 0x01b7,
702 [ C(RESULT_MISS) ] = 0x01b7,
704 [ C(OP_PREFETCH) ] = {
706 [ C(RESULT_ACCESS) ] = 0x01b7,
708 [ C(RESULT_MISS) ] = 0x01b7,
711 [ C(DTLB) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
714 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
718 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x0,
722 [ C(RESULT_MISS) ] = 0x0,
725 [ C(ITLB) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
728 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = -1,
732 [ C(RESULT_MISS) ] = -1,
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
739 [ C(BPU ) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
742 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = -1,
746 [ C(RESULT_MISS) ] = -1,
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = -1,
750 [ C(RESULT_MISS) ] = -1,
753 [ C(NODE) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x01b7,
756 [ C(RESULT_MISS) ] = 0x01b7,
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = 0x01b7,
760 [ C(RESULT_MISS) ] = 0x01b7,
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = 0x01b7,
764 [ C(RESULT_MISS) ] = 0x01b7,
819 [ C(L1D ) ] = {
820 [ C(OP_READ) ] = {
821 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
822 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
824 [ C(OP_WRITE) ] = {
825 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
826 [ C(RESULT_MISS) ] = 0x0,
828 [ C(OP_PREFETCH) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0,
830 [ C(RESULT_MISS) ] = 0x0,
833 [ C(L1I ) ] = {
834 [ C(OP_READ) ] = {
835 [ C(RESULT_ACCESS) ] = 0x0,
836 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
838 [ C(OP_WRITE) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
842 [ C(OP_PREFETCH) ] = {
843 [ C(RESULT_ACCESS) ] = 0x0,
844 [ C(RESULT_MISS) ] = 0x0,
847 [ C(LL ) ] = {
848 [ C(OP_READ) ] = {
849 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
850 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
852 [ C(OP_WRITE) ] = {
853 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
854 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
856 [ C(OP_PREFETCH) ] = {
857 [ C(RESULT_ACCESS) ] = 0x0,
858 [ C(RESULT_MISS) ] = 0x0,
861 [ C(DTLB) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
864 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
868 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
870 [ C(OP_PREFETCH) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0,
875 [ C(ITLB) ] = {
876 [ C(OP_READ) ] = {
877 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
878 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
880 [ C(OP_WRITE) ] = {
881 [ C(RESULT_ACCESS) ] = -1,
882 [ C(RESULT_MISS) ] = -1,
884 [ C(OP_PREFETCH) ] = {
885 [ C(RESULT_ACCESS) ] = -1,
886 [ C(RESULT_MISS) ] = -1,
889 [ C(BPU ) ] = {
890 [ C(OP_READ) ] = {
891 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
892 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
894 [ C(OP_WRITE) ] = {
895 [ C(RESULT_ACCESS) ] = -1,
896 [ C(RESULT_MISS) ] = -1,
898 [ C(OP_PREFETCH) ] = {
899 [ C(RESULT_ACCESS) ] = -1,
900 [ C(RESULT_MISS) ] = -1,
903 [ C(NODE) ] = {
904 [ C(OP_READ) ] = {
905 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
906 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
908 [ C(OP_WRITE) ] = {
909 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
910 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
912 [ C(OP_PREFETCH) ] = {
913 [ C(RESULT_ACCESS) ] = 0x0,
914 [ C(RESULT_MISS) ] = 0x0,
924 [ C(LL ) ] = {
925 [ C(OP_READ) ] = {
926 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
928 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
934 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
937 [ C(OP_PREFETCH) ] = {
938 [ C(RESULT_ACCESS) ] = 0x0,
939 [ C(RESULT_MISS) ] = 0x0,
942 [ C(NODE) ] = {
943 [ C(OP_READ) ] = {
944 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
947 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
951 [ C(OP_WRITE) ] = {
952 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
955 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
959 [ C(OP_PREFETCH) ] = {
960 [ C(RESULT_ACCESS) ] = 0x0,
961 [ C(RESULT_MISS) ] = 0x0,
971 [ C(L1D) ] = {
972 [ C(OP_READ) ] = {
973 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
974 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
976 [ C(OP_WRITE) ] = {
977 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
978 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
980 [ C(OP_PREFETCH) ] = {
981 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
982 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
985 [ C(L1I ) ] = {
986 [ C(OP_READ) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
988 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
990 [ C(OP_WRITE) ] = {
991 [ C(RESULT_ACCESS) ] = -1,
992 [ C(RESULT_MISS) ] = -1,
994 [ C(OP_PREFETCH) ] = {
995 [ C(RESULT_ACCESS) ] = 0x0,
996 [ C(RESULT_MISS) ] = 0x0,
999 [ C(LL ) ] = {
1000 [ C(OP_READ) ] = {
1002 [ C(RESULT_ACCESS) ] = 0x01b7,
1004 [ C(RESULT_MISS) ] = 0x01b7,
1010 [ C(OP_WRITE) ] = {
1012 [ C(RESULT_ACCESS) ] = 0x01b7,
1014 [ C(RESULT_MISS) ] = 0x01b7,
1016 [ C(OP_PREFETCH) ] = {
1018 [ C(RESULT_ACCESS) ] = 0x01b7,
1020 [ C(RESULT_MISS) ] = 0x01b7,
1023 [ C(DTLB) ] = {
1024 [ C(OP_READ) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1026 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1028 [ C(OP_WRITE) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1030 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1032 [ C(OP_PREFETCH) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x0,
1034 [ C(RESULT_MISS) ] = 0x0,
1037 [ C(ITLB) ] = {
1038 [ C(OP_READ) ] = {
1039 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1040 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1042 [ C(OP_WRITE) ] = {
1043 [ C(RESULT_ACCESS) ] = -1,
1044 [ C(RESULT_MISS) ] = -1,
1046 [ C(OP_PREFETCH) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1051 [ C(BPU ) ] = {
1052 [ C(OP_READ) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1054 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1056 [ C(OP_WRITE) ] = {
1057 [ C(RESULT_ACCESS) ] = -1,
1058 [ C(RESULT_MISS) ] = -1,
1060 [ C(OP_PREFETCH) ] = {
1061 [ C(RESULT_ACCESS) ] = -1,
1062 [ C(RESULT_MISS) ] = -1,
1065 [ C(NODE) ] = {
1066 [ C(OP_READ) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x01b7,
1068 [ C(RESULT_MISS) ] = 0x01b7,
1070 [ C(OP_WRITE) ] = {
1071 [ C(RESULT_ACCESS) ] = 0x01b7,
1072 [ C(RESULT_MISS) ] = 0x01b7,
1074 [ C(OP_PREFETCH) ] = {
1075 [ C(RESULT_ACCESS) ] = 0x01b7,
1076 [ C(RESULT_MISS) ] = 0x01b7,
1119 [ C(LL ) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1122 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1126 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1130 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1133 [ C(NODE) ] = {
1134 [ C(OP_READ) ] = {
1135 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1136 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1138 [ C(OP_WRITE) ] = {
1139 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1140 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1142 [ C(OP_PREFETCH) ] = {
1143 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1144 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1154 [ C(L1D) ] = {
1155 [ C(OP_READ) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1157 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1159 [ C(OP_WRITE) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1161 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1163 [ C(OP_PREFETCH) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1165 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1168 [ C(L1I ) ] = {
1169 [ C(OP_READ) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1171 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1173 [ C(OP_WRITE) ] = {
1174 [ C(RESULT_ACCESS) ] = -1,
1175 [ C(RESULT_MISS) ] = -1,
1177 [ C(OP_PREFETCH) ] = {
1178 [ C(RESULT_ACCESS) ] = 0x0,
1179 [ C(RESULT_MISS) ] = 0x0,
1182 [ C(LL ) ] = {
1183 [ C(OP_READ) ] = {
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1187 [ C(RESULT_MISS) ] = 0x01b7,
1193 [ C(OP_WRITE) ] = {
1195 [ C(RESULT_ACCESS) ] = 0x01b7,
1197 [ C(RESULT_MISS) ] = 0x01b7,
1199 [ C(OP_PREFETCH) ] = {
1201 [ C(RESULT_ACCESS) ] = 0x01b7,
1203 [ C(RESULT_MISS) ] = 0x01b7,
1206 [ C(DTLB) ] = {
1207 [ C(OP_READ) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1209 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1211 [ C(OP_WRITE) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1213 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1215 [ C(OP_PREFETCH) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x0,
1217 [ C(RESULT_MISS) ] = 0x0,
1220 [ C(ITLB) ] = {
1221 [ C(OP_READ) ] = {
1222 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1223 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1225 [ C(OP_WRITE) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1229 [ C(OP_PREFETCH) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1234 [ C(BPU ) ] = {
1235 [ C(OP_READ) ] = {
1236 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1237 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1239 [ C(OP_WRITE) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1243 [ C(OP_PREFETCH) ] = {
1244 [ C(RESULT_ACCESS) ] = -1,
1245 [ C(RESULT_MISS) ] = -1,
1248 [ C(NODE) ] = {
1249 [ C(OP_READ) ] = {
1250 [ C(RESULT_ACCESS) ] = 0x01b7,
1251 [ C(RESULT_MISS) ] = 0x01b7,
1253 [ C(OP_WRITE) ] = {
1254 [ C(RESULT_ACCESS) ] = 0x01b7,
1255 [ C(RESULT_MISS) ] = 0x01b7,
1257 [ C(OP_PREFETCH) ] = {
1258 [ C(RESULT_ACCESS) ] = 0x01b7,
1259 [ C(RESULT_MISS) ] = 0x01b7,
1269 [ C(L1D) ] = {
1270 [ C(OP_READ) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1272 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1274 [ C(OP_WRITE) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1276 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1278 [ C(OP_PREFETCH) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1280 [ C(RESULT_MISS) ] = 0,
1283 [ C(L1I ) ] = {
1284 [ C(OP_READ) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1286 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1288 [ C(OP_WRITE) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1292 [ C(OP_PREFETCH) ] = {
1293 [ C(RESULT_ACCESS) ] = 0,
1294 [ C(RESULT_MISS) ] = 0,
1297 [ C(LL ) ] = {
1298 [ C(OP_READ) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1300 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1302 [ C(OP_WRITE) ] = {
1303 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1304 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1306 [ C(OP_PREFETCH) ] = {
1307 [ C(RESULT_ACCESS) ] = 0,
1308 [ C(RESULT_MISS) ] = 0,
1311 [ C(DTLB) ] = {
1312 [ C(OP_READ) ] = {
1313 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1314 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1316 [ C(OP_WRITE) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1318 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1320 [ C(OP_PREFETCH) ] = {
1321 [ C(RESULT_ACCESS) ] = 0,
1322 [ C(RESULT_MISS) ] = 0,
1325 [ C(ITLB) ] = {
1326 [ C(OP_READ) ] = {
1327 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1328 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1330 [ C(OP_WRITE) ] = {
1331 [ C(RESULT_ACCESS) ] = -1,
1332 [ C(RESULT_MISS) ] = -1,
1334 [ C(OP_PREFETCH) ] = {
1335 [ C(RESULT_ACCESS) ] = -1,
1336 [ C(RESULT_MISS) ] = -1,
1339 [ C(BPU ) ] = {
1340 [ C(OP_READ) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1342 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1344 [ C(OP_WRITE) ] = {
1345 [ C(RESULT_ACCESS) ] = -1,
1346 [ C(RESULT_MISS) ] = -1,
1348 [ C(OP_PREFETCH) ] = {
1349 [ C(RESULT_ACCESS) ] = -1,
1350 [ C(RESULT_MISS) ] = -1,
1360 [ C(L1D) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1363 [ C(RESULT_MISS) ] = 0,
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1367 [ C(RESULT_MISS) ] = 0,
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = 0x0,
1371 [ C(RESULT_MISS) ] = 0,
1374 [ C(L1I ) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1377 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = 0,
1385 [ C(RESULT_MISS) ] = 0,
1388 [ C(LL ) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1391 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1395 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0,
1399 [ C(RESULT_MISS) ] = 0,
1402 [ C(DTLB) ] = {
1403 [ C(OP_READ) ] = {
1404 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1405 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1407 [ C(OP_WRITE) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1409 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1411 [ C(OP_PREFETCH) ] = {
1412 [ C(RESULT_ACCESS) ] = 0,
1413 [ C(RESULT_MISS) ] = 0,
1416 [ C(ITLB) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1419 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = -1,
1423 [ C(RESULT_MISS) ] = -1,
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1430 [ C(BPU ) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1433 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1490 [ C(LL ) ] = {
1491 [ C(OP_READ) ] = {
1492 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1493 [ C(RESULT_MISS) ] = 0,
1495 [ C(OP_WRITE) ] = {
1496 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1497 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1499 [ C(OP_PREFETCH) ] = {
1500 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1501 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1511 [ C(L1D) ] = {
1512 [ C(OP_READ) ] = {
1513 [ C(RESULT_ACCESS) ] = 0,
1514 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1516 [ C(OP_WRITE) ] = {
1517 [ C(RESULT_ACCESS) ] = 0,
1518 [ C(RESULT_MISS) ] = 0,
1520 [ C(OP_PREFETCH) ] = {
1521 [ C(RESULT_ACCESS) ] = 0,
1522 [ C(RESULT_MISS) ] = 0,
1525 [ C(L1I ) ] = {
1526 [ C(OP_READ) ] = {
1527 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1528 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1530 [ C(OP_WRITE) ] = {
1531 [ C(RESULT_ACCESS) ] = -1,
1532 [ C(RESULT_MISS) ] = -1,
1534 [ C(OP_PREFETCH) ] = {
1535 [ C(RESULT_ACCESS) ] = 0,
1536 [ C(RESULT_MISS) ] = 0,
1539 [ C(LL ) ] = {
1540 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x01b7,
1543 [ C(RESULT_MISS) ] = 0,
1545 [ C(OP_WRITE) ] = {
1547 [ C(RESULT_ACCESS) ] = 0x01b7,
1549 [ C(RESULT_MISS) ] = 0x01b7,
1551 [ C(OP_PREFETCH) ] = {
1553 [ C(RESULT_ACCESS) ] = 0x01b7,
1555 [ C(RESULT_MISS) ] = 0x01b7,
1558 [ C(DTLB) ] = {
1559 [ C(OP_READ) ] = {
1560 [ C(RESULT_ACCESS) ] = 0,
1561 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1563 [ C(OP_WRITE) ] = {
1564 [ C(RESULT_ACCESS) ] = 0,
1565 [ C(RESULT_MISS) ] = 0,
1567 [ C(OP_PREFETCH) ] = {
1568 [ C(RESULT_ACCESS) ] = 0,
1569 [ C(RESULT_MISS) ] = 0,
1572 [ C(ITLB) ] = {
1573 [ C(OP_READ) ] = {
1574 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1575 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1577 [ C(OP_WRITE) ] = {
1578 [ C(RESULT_ACCESS) ] = -1,
1579 [ C(RESULT_MISS) ] = -1,
1581 [ C(OP_PREFETCH) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1586 [ C(BPU ) ] = {
1587 [ C(OP_READ) ] = {
1588 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1589 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1591 [ C(OP_WRITE) ] = {
1592 [ C(RESULT_ACCESS) ] = -1,
1593 [ C(RESULT_MISS) ] = -1,
1595 [ C(OP_PREFETCH) ] = {
1596 [ C(RESULT_ACCESS) ] = -1,
1597 [ C(RESULT_MISS) ] = -1,
1645 [C(L1D)] = {
1646 [C(OP_READ)] = {
1647 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1648 [C(RESULT_MISS)] = 0x0,
1650 [C(OP_WRITE)] = {
1651 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1652 [C(RESULT_MISS)] = 0x0,
1654 [C(OP_PREFETCH)] = {
1655 [C(RESULT_ACCESS)] = 0x0,
1656 [C(RESULT_MISS)] = 0x0,
1659 [C(L1I)] = {
1660 [C(OP_READ)] = {
1661 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1662 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1664 [C(OP_WRITE)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1668 [C(OP_PREFETCH)] = {
1669 [C(RESULT_ACCESS)] = 0x0,
1670 [C(RESULT_MISS)] = 0x0,
1673 [C(LL)] = {
1674 [C(OP_READ)] = {
1675 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1676 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1678 [C(OP_WRITE)] = {
1679 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1680 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1682 [C(OP_PREFETCH)] = {
1683 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1684 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1687 [C(DTLB)] = {
1688 [C(OP_READ)] = {
1689 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1690 [C(RESULT_MISS)] = 0x0,
1692 [C(OP_WRITE)] = {
1693 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1694 [C(RESULT_MISS)] = 0x0,
1696 [C(OP_PREFETCH)] = {
1697 [C(RESULT_ACCESS)] = 0x0,
1698 [C(RESULT_MISS)] = 0x0,
1701 [C(ITLB)] = {
1702 [C(OP_READ)] = {
1703 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1704 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1706 [C(OP_WRITE)] = {
1707 [C(RESULT_ACCESS)] = -1,
1708 [C(RESULT_MISS)] = -1,
1710 [C(OP_PREFETCH)] = {
1711 [C(RESULT_ACCESS)] = -1,
1712 [C(RESULT_MISS)] = -1,
1715 [C(BPU)] = {
1716 [C(OP_READ)] = {
1717 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1718 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1720 [C(OP_WRITE)] = {
1721 [C(RESULT_ACCESS)] = -1,
1722 [C(RESULT_MISS)] = -1,
1724 [C(OP_PREFETCH)] = {
1725 [C(RESULT_ACCESS)] = -1,
1726 [C(RESULT_MISS)] = -1,
1735 [C(LL)] = {
1736 [C(OP_READ)] = {
1737 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1739 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1742 [C(OP_WRITE)] = {
1743 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1745 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1748 [C(OP_PREFETCH)] = {
1749 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1751 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1761 [C(L1D)] = {
1762 [C(OP_READ)] = {
1763 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1764 [C(RESULT_MISS)] = 0x0,
1766 [C(OP_WRITE)] = {
1767 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1768 [C(RESULT_MISS)] = 0x0,
1770 [C(OP_PREFETCH)] = {
1771 [C(RESULT_ACCESS)] = 0x0,
1772 [C(RESULT_MISS)] = 0x0,
1775 [C(L1I)] = {
1776 [C(OP_READ)] = {
1777 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1778 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1780 [C(OP_WRITE)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1784 [C(OP_PREFETCH)] = {
1785 [C(RESULT_ACCESS)] = 0x0,
1786 [C(RESULT_MISS)] = 0x0,
1789 [C(LL)] = {
1790 [C(OP_READ)] = {
1791 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1792 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1794 [C(OP_WRITE)] = {
1795 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1796 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1798 [C(OP_PREFETCH)] = {
1799 [C(RESULT_ACCESS)] = 0x0,
1800 [C(RESULT_MISS)] = 0x0,
1803 [C(DTLB)] = {
1804 [C(OP_READ)] = {
1805 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1806 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1808 [C(OP_WRITE)] = {
1809 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1810 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1812 [C(OP_PREFETCH)] = {
1813 [C(RESULT_ACCESS)] = 0x0,
1814 [C(RESULT_MISS)] = 0x0,
1817 [C(ITLB)] = {
1818 [C(OP_READ)] = {
1819 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1820 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1822 [C(OP_WRITE)] = {
1823 [C(RESULT_ACCESS)] = -1,
1824 [C(RESULT_MISS)] = -1,
1826 [C(OP_PREFETCH)] = {
1827 [C(RESULT_ACCESS)] = -1,
1828 [C(RESULT_MISS)] = -1,
1831 [C(BPU)] = {
1832 [C(OP_READ)] = {
1833 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1834 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1836 [C(OP_WRITE)] = {
1837 [C(RESULT_ACCESS)] = -1,
1838 [C(RESULT_MISS)] = -1,
1840 [C(OP_PREFETCH)] = {
1841 [C(RESULT_ACCESS)] = -1,
1842 [C(RESULT_MISS)] = -1,
1851 [C(LL)] = {
1852 [C(OP_READ)] = {
1853 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1855 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1858 [C(OP_WRITE)] = {
1859 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1861 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1864 [C(OP_PREFETCH)] = {
1865 [C(RESULT_ACCESS)] = 0x0,
1866 [C(RESULT_MISS)] = 0x0,
1883 [C(LL)] = {
1884 [C(OP_READ)] = {
1885 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1887 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1890 [C(OP_WRITE)] = {
1891 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1893 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1896 [C(OP_PREFETCH)] = {
1897 [C(RESULT_ACCESS)] = 0x0,
1898 [C(RESULT_MISS)] = 0x0,
1930 [C(LL)] = {
1931 [C(OP_READ)] = {
1932 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1933 [C(RESULT_MISS)] = 0,
1935 [C(OP_WRITE)] = {
1936 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1937 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1939 [C(OP_PREFETCH)] = {
1940 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1941 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
5161 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
5258 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
5334 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
5336 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
5338 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
5340 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
5448 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()