Lines Matching +full:0 +full:x7
8 #define load_8way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
9 vmovdqu (0*16)(src), x0; \
16 vmovdqu (7*16)(src), x7;
18 #define store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
19 vmovdqu x0, (0*16)(dst); \
26 vmovdqu x7, (7*16)(dst);
28 #define store_cbc_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
29 vpxor (0*16)(src), x1, x1; \
35 vpxor (6*16)(src), x7, x7; \
36 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
44 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \ argument
46 vpsrldq $8, t0, t0; /* low: -1, high: 0 */ \
50 vmovdqu (iv), x7; \
51 vpshufb t1, x7, x0; \
54 inc_le128(x7, t0, t2); \
55 vpshufb t1, x7, x1; \
56 inc_le128(x7, t0, t2); \
57 vpshufb t1, x7, x2; \
58 inc_le128(x7, t0, t2); \
59 vpshufb t1, x7, x3; \
60 inc_le128(x7, t0, t2); \
61 vpshufb t1, x7, x4; \
62 inc_le128(x7, t0, t2); \
63 vpshufb t1, x7, x5; \
64 inc_le128(x7, t0, t2); \
65 vpshufb t1, x7, x6; \
66 inc_le128(x7, t0, t2); \
67 vmovdqa x7, t2; \
68 vpshufb t1, x7, x7; \
72 #define store_ctr_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
73 vpxor (0*16)(src), x0, x0; \
80 vpxor (7*16)(src), x7, x7; \
81 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
86 vpshufd $0x13, tmp, tmp; \
90 #define load_xts_8way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, t0, \ argument
96 vpxor (0*16)(src), tiv, x0; \
97 vmovdqu tiv, (0*16)(dst); \
125 vpxor (7*16)(src), tiv, x7; \
131 #define store_xts_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
132 vpxor (0*16)(dst), x0, x0; \
139 vpxor (7*16)(dst), x7, x7; \
140 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);