1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/apb.h>
112 #define  SABRE_PCICTRL_ARBPARK	 0x0000000000200000UL	/* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
113 #define  SABRE_PCICTRL_CPUPRIO	 0x0000000000100000UL	/* Ultra-IIi granted every other bus cycle */
116 #define  SABRE_PCICTRL_RTRYWE	 0x0000000000000080UL	/* DMA Flow Control 0=wait-if-possible 1=retry …
135 #define  SABRE_PCIDIAG_ELPBK	 0x0000000000000001UL	/* Loopback Enable - not supported */
137 #define  SABRE_PCITASR_EF	 0x0000000000000080UL	/* Respond to 0xe0000000-0xffffffff */
138 #define  SABRE_PCITASR_CD	 0x0000000000000040UL	/* Respond to 0xc0000000-0xdfffffff */
139 #define  SABRE_PCITASR_AB	 0x0000000000000020UL	/* Respond to 0xa0000000-0xbfffffff */
140 #define  SABRE_PCITASR_89	 0x0000000000000010UL	/* Respond to 0x80000000-0x9fffffff */
141 #define  SABRE_PCITASR_67	 0x0000000000000008UL	/* Respond to 0x60000000-0x7fffffff */
142 #define  SABRE_PCITASR_45	 0x0000000000000004UL	/* Respond to 0x40000000-0x5fffffff */
143 #define  SABRE_PCITASR_23	 0x0000000000000002UL	/* Respond to 0x20000000-0x3fffffff */
144 #define  SABRE_PCITASR_01	 0x0000000000000001UL	/* Respond to 0x00000000-0x1fffffff */
156 #define  SABRE_IOMMUTAG_STREAM	 0x0000000000100000UL	/* Streamable bit - unused */
172 #define  SABRE_MCCTRL0_11BIT	 0x0000000000001000	/* Enable 11-bit column addressing */
200 	unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;  in sabre_ue_intr()
201 	unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;  in sabre_ue_intr()
220 	       pbm->name,  in sabre_ue_intr()
228 	       pbm->name,  in sabre_ue_intr()
232 	printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);  in sabre_ue_intr()
233 	printk("%s: UE Secondary errors [", pbm->name);  in sabre_ue_intr()
260 	unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;  in sabre_ce_intr()
261 	unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;  in sabre_ce_intr()
279 	       pbm->name,  in sabre_ce_intr()
286 	 * XXX UDB CE trap handler does... -DaveM  in sabre_ce_intr()
290 	       pbm->name,  in sabre_ce_intr()
295 	printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);  in sabre_ce_intr()
296 	printk("%s: CE Secondary errors [", pbm->name);  in sabre_ce_intr()
315 	struct device_node *dp = pbm->op->dev.of_node;  in sabre_register_error_handlers()
317 	unsigned long base = pbm->controller_regs;  in sabre_register_error_handlers()  local
321 	if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)  in sabre_register_error_handlers()
322 		dp = dp->parent;  in sabre_register_error_handlers()
334 	if (op->archdata.num_irqs < 4)  in sabre_register_error_handlers()
344 		   base + SABRE_UE_AFSR);  in sabre_register_error_handlers()
346 	err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);  in sabre_register_error_handlers()
349 		       pbm->name, err);  in sabre_register_error_handlers()
353 		   base + SABRE_CE_AFSR);  in sabre_register_error_handlers()
356 	err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);  in sabre_register_error_handlers()
359 		       pbm->name, err);  in sabre_register_error_handlers()
360 	err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,  in sabre_register_error_handlers()
364 		       pbm->name, err);  in sabre_register_error_handlers()
366 	tmp = upa_readq(base + SABRE_PCICTRL);  in sabre_register_error_handlers()
368 	upa_writeq(tmp, base + SABRE_PCICTRL);  in sabre_register_error_handlers()
375 	list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {  in apb_init()
376 		if (pdev->vendor == PCI_VENDOR_ID_SUN &&  in apb_init()
377 		    pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {  in apb_init()
411 	/* The APB bridge speaks to the Sabre host PCI bridge  in sabre_scan_bus()
412 	 * at 66Mhz, but the front side of APB runs at 33Mhz  in sabre_scan_bus()
415 	 * Hummingbird systems do not use APB, so they run  in sabre_scan_bus()
419 		pbm->is_66mhz_capable = 1;  in sabre_scan_bus()
421 		pbm->is_66mhz_capable = 0;  in sabre_scan_bus()
435 	pbm->pci_bus = pci_scan_one_pbm(pbm, parent);  in sabre_scan_bus()
436 	if (!pbm->pci_bus)  in sabre_scan_bus()
439 	sabre_root_bus = pbm->pci_bus;  in sabre_scan_bus()
441 	apb_init(pbm->pci_bus);  in sabre_scan_bus()
450 	pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;  in sabre_pbm_init()
451 	pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;  in sabre_pbm_init()
452 	pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;  in sabre_pbm_init()
453 	sabre_scan_bus(pbm, &op->dev);  in sabre_pbm_init()
461 	struct device_node *dp = op->dev.of_node;  in sabre_probe()
469 	match = of_match_device(sabre_match, &op->dev);  in sabre_probe()
470 	hummingbird_p = match && (match->data != NULL);  in sabre_probe()
478 			if (of_node_name_eq(cpu_dp, "SUNW,UltraSPARC-IIe"))  in sabre_probe()
483 	err = -ENOMEM;  in sabre_probe()
496 	pbm->iommu = iommu;  in sabre_probe()
498 	upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);  in sabre_probe()
500 	pbm->portid = upa_portid;  in sabre_probe()
507 	err = -ENODEV;  in sabre_probe()
514 	 * First REG in property is base of entire SABRE register space.  in sabre_probe()
516 	pbm->controller_regs = pr_regs[0].phys_addr;  in sabre_probe()
522 		upa_writeq(0x0UL, pbm->controller_regs + clear_irq);  in sabre_probe()
526 		upa_writeq(0x0UL, pbm->controller_regs + clear_irq);  in sabre_probe()
531 		   pbm->controller_regs + SABRE_PCICTRL);  in sabre_probe()
534 	pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;  in sabre_probe()
536 	vdma = of_get_property(dp, "virtual-dma", NULL);  in sabre_probe()
538 		printk(KERN_ERR PFX "No virtual-dma property\n");  in sabre_probe()
558 			printk(KERN_ERR PFX "Strange virtual-dma size.\n");  in sabre_probe()
567 	 * Look for APB underneath.  in sabre_probe()
571 	pbm->next = pci_pbm_root;  in sabre_probe()
574 	dev_set_drvdata(&op->dev, pbm);  in sabre_probe()
579 	kfree(pbm->iommu);  in sabre_probe()