Lines Matching refs:g2
13 sethi %hi(cheetah_fast_ecc), %g2
14 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
26 sethi %hi(cheetah_fast_ecc), %g2
27 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
39 sethi %hi(cheetah_cee), %g2
40 jmpl %g2 + %lo(cheetah_cee), %g0
52 sethi %hi(cheetah_cee), %g2
53 jmpl %g2 + %lo(cheetah_cee), %g0
65 sethi %hi(cheetah_deferred_trap), %g2
66 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
78 sethi %hi(cheetah_deferred_trap), %g2
79 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
105 rdpr %pil, %g2
147 rdpr %pil, %g2
183 mov 1, %g2 ! Setup TSTATE checking loop
185 1: wrpr %g2, %tl ! Set trap level to check
190 add %g2, 1, %g2 ! Next trap level
191 cmp %g2, %g1 ! Hit them all yet?
196 sethi %hi(dcache_parity_tl1_occurred), %g2
197 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
199 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
202 mov (1 << 5), %g2 ! D-cache line size
203 sub %g1, %g2, %g1 ! Move down 1 cacheline
208 sub %g2, 8, %g3 ! 64-bit data word within line
215 subcc %g1, %g2, %g1 ! Next cacheline
234 mov 1, %g2 ! Setup TSTATE checking loop
236 1: wrpr %g2, %tl ! Set trap level to check
241 add %g2, 1, %g2 ! Next trap level
242 cmp %g2, %g1 ! Hit them all yet?
247 sethi %hi(icache_parity_tl1_occurred), %g2
248 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
250 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
253 mov (1 << 5), %g2 ! I-cache line size
254 sub %g1, %g2, %g1
258 subcc %g1, %g2, %g1
279 mov (1 << 5), %g2 ! D-cache line size
280 sub %g1, %g2, %g1
283 subcc %g1, %g2, %g1
307 sllx %g1, 63, %g2
308 or %g4, %g2, %g4
311 BRANCH_IF_JALAPENO(g2,g3,50f)
312 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
313 srlx %g2, 17, %g2
315 and %g2, 0x3ff, %g2
317 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
318 srlx %g2, 17, %g2
319 and %g2, 0x1f, %g2
321 60: sllx %g2, 9, %g2
327 add %g3, %g2, %g3
342 set 0x3ff8, %g2 /* DC_addr mask */
343 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
347 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
353 stx %g2, [%g1 + 0x20]
358 ldxa [%g2] ASI_DCACHE_UTAG, %g7
361 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
365 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
376 add %g2, %g7, %g2
377 srlx %g2, 14, %g7
385 20: set 0x1fe0, %g2 /* IC_addr mask */
386 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
387 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
391 21: ldxa [%g2] ASI_IC_TAG, %g7
398 stx %g2, [%g1 + 0x40]
400 add %g2, (1 << 3), %g2
401 ldxa [%g2] ASI_IC_TAG, %g7
402 add %g2, (1 << 3), %g2
404 ldxa [%g2] ASI_IC_TAG, %g7
405 add %g2, (1 << 3), %g2
407 ldxa [%g2] ASI_IC_TAG, %g7
409 sub %g2, (3 << 3), %g2
410 ldxa [%g2] ASI_IC_STAG, %g7
413 srlx %g2, 2, %g2
415 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
426 add %g2, %g7, %g2
427 srlx %g2, 14, %g7
435 30: andn %g5, (32 - 1), %g2
436 stx %g2, [%g1 + 0x20]
437 ldxa [%g2] ASI_EC_TAG_DATA, %g7
439 ldxa [%g2] ASI_EC_R, %g0
450 rdpr %tt, %g2
451 cmp %g2, 0x70
453 cmp %g2, 0x63
474 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
475 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
476 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
491 rdpr %pil, %g2
510 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
511 andn %g2, ESTATE_ERROR_CEEN, %g2
512 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
527 rdpr %pil, %g2
546 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
547 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
548 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
563 rdpr %pil, %g2