Lines Matching +full:0 +full:x740
35 DEFINE_RES_MEM(0xffea0000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x700)),
37 DEFINE_RES_IRQ(evt2irq(0x720)),
38 DEFINE_RES_IRQ(evt2irq(0x760)),
39 DEFINE_RES_IRQ(evt2irq(0x740)),
44 .id = 0,
62 DEFINE_RES_MEM(0xffeb0000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x780)),
67 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(0),
70 DEFINE_RES_IRQ(0),
71 DEFINE_RES_IRQ(0),
72 DEFINE_RES_IRQ(0),
92 DEFINE_RES_MEM(0xffec0000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x840)),
113 DEFINE_RES_MEM(0xffed0000, 0x100),
114 DEFINE_RES_IRQ(evt2irq(0x860)),
134 DEFINE_RES_MEM(0xffee0000, 0x100),
135 DEFINE_RES_IRQ(evt2irq(0x880)),
155 DEFINE_RES_MEM(0xffef0000, 0x100),
156 DEFINE_RES_IRQ(evt2irq(0x8a0)),
174 DEFINE_RES_MEM(0xffd80000, 0x30),
175 DEFINE_RES_IRQ(evt2irq(0x400)),
176 DEFINE_RES_IRQ(evt2irq(0x420)),
177 DEFINE_RES_IRQ(evt2irq(0x440)),
182 .id = 0,
195 DEFINE_RES_MEM(0xffda0000, 0x2c),
196 DEFINE_RES_IRQ(evt2irq(0x480)),
197 DEFINE_RES_IRQ(evt2irq(0x4a0)),
198 DEFINE_RES_IRQ(evt2irq(0x4c0)),
216 DEFINE_RES_MEM(0xffdc0000, 0x2c),
217 DEFINE_RES_IRQ(evt2irq(0x7a0)),
218 DEFINE_RES_IRQ(evt2irq(0x7a0)),
219 DEFINE_RES_IRQ(evt2irq(0x7a0)),
237 DEFINE_RES_MEM(0xffde0000, 0x2c),
238 DEFINE_RES_IRQ(evt2irq(0x7c0)),
239 DEFINE_RES_IRQ(evt2irq(0x7c0)),
240 DEFINE_RES_IRQ(evt2irq(0x7c0)),
255 .offset = 0,
256 .dmars = 0,
257 .dmars_bit = 0,
259 .offset = 0x10,
260 .dmars = 0,
263 .offset = 0x20,
265 .dmars_bit = 0,
267 .offset = 0x30,
271 .offset = 0x50,
273 .dmars_bit = 0,
275 .offset = 0x60,
299 .start = 0xfe008020,
300 .end = 0xfe00808f,
304 .start = 0xfe009000,
305 .end = 0xfe00900b,
309 .start = evt2irq(0x5c0),
310 .end = evt2irq(0x5c0),
313 /* IRQ for channels 0-5 */
314 .start = evt2irq(0x500),
315 .end = evt2irq(0x5a0),
322 .id = 0,
330 #define USB_EHCI_START 0xffe70000
331 #define USB_OHCI_START 0xffe70400
334 [0] = {
336 .end = USB_EHCI_START + 0x3ff,
340 .start = evt2irq(0xba0),
341 .end = evt2irq(0xba0),
358 [0] = {
360 .end = USB_OHCI_START + 0x3ff,
364 .start = evt2irq(0xba0),
365 .end = evt2irq(0xba0),
407 #define USBCTL0 0xffe70858
408 #define CLOCK_MODE_MASK 0xffffff7f
409 #define EXT_CLOCK_MODE 0x00000080
417 #define USBINITREG1 0xffe70094
418 #define USBINITREG2 0xffe7009c
419 #define USBINITVAL1 0x00ff0040
420 #define USBINITVAL2 0x00000001
422 #define USBPCTL1 0xffe70804
423 #define USBST 0xffe70808
424 #define PHY_ENB 0x00000001
425 #define PLL_ENB 0x00000002
426 #define PHY_RST 0x00000004
427 #define ACT_PLL_STATUS 0xc0000000
460 UNUSED = 0,
506 INTC_VECT(WDT, 0x3e0),
507 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
508 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
509 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
510 INTC_VECT(TMU1_2, 0x4c0),
511 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
512 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
513 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
514 INTC_VECT(DMAC0_6, 0x5c0),
515 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
516 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
517 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
518 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
519 INTC_VECT(HPB_2, 0x6e0),
520 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
521 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
522 INTC_VECT(SCIF1, 0x780),
523 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
524 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
525 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
526 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
527 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
528 INTC_VECT(PCIeC0_2, 0xb20),
529 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
530 INTC_VECT(PCIeC1_2, 0xb80),
531 INTC_VECT(USB, 0xba0),
532 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
533 INTC_VECT(DU, 0xd00),
534 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
535 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
536 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
537 INTC_VECT(PCIeC2_2, 0xde0),
538 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
539 INTC_VECT(FLCTL, 0xe40),
540 INTC_VECT(HSPI, 0xe80),
541 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
542 INTC_VECT(Thermal, 0xee0),
543 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
544 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
545 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
546 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
549 #define CnINTMSK0 0xfe410030
550 #define CnINTMSK1 0xfe410040
551 #define CnINTMSKCLR0 0xfe410050
552 #define CnINTMSKCLR1 0xfe410060
553 #define CnINT2MSKR0 0xfe410a20
554 #define CnINT2MSKR1 0xfe410a24
555 #define CnINT2MSKR2 0xfe410a28
556 #define CnINT2MSKR3 0xfe410a2c
557 #define CnINT2MSKCR0 0xfe410a30
558 #define CnINT2MSKCR1 0xfe410a34
559 #define CnINT2MSKCR2 0xfe410a38
560 #define CnINT2MSKCR3 0xfe410a3c
561 #define INTMSK2 0xfe410068
562 #define INTMSKCLR2 0xfe41006c
564 #define INTDISTCR0 0xfe4100b0
565 #define INTDISTCR1 0xfe4100b4
566 #define INT2DISTCR0 0xfe410900
567 #define INT2DISTCR1 0xfe410904
568 #define INT2DISTCR2 0xfe410908
569 #define INT2DISTCR3 0xfe41090c
579 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
583 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
585 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
589 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
596 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
598 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
603 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
605 { 0, 0, 0, 0, 0, 0,
610 FLCTL, 0,
612 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
616 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
618 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
619 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
621 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
622 TMU1_2, 0 } },
623 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
625 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
627 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
629 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
631 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
633 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
634 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
635 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
637 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
638 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
639 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
640 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
641 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
643 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
644 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
645 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
646 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
647 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
649 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
650 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
652 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
653 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
654 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
660 { 0xfe410c20, 32, SCIF1,
661 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
681 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
682 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
686 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
687 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
691 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
696 { 0xfe410024, 0, 32, /* INTREQ */
713 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
714 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
715 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
716 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
717 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
718 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
719 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
720 INTC_VECT(IRL0_HHHL, 0x3c0),
724 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
725 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
726 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
727 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
728 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
729 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
730 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
731 INTC_VECT(IRL4_HHHL, 0xac0),
740 #define INTC_ICR0 0xfe410000
749 /* disable IRQ3-0 + IRQ7-4 */ in plat_irq_setup()
750 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
752 /* disable IRL3-0 + IRL7-4 */ in plat_irq_setup()
753 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
754 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
756 /* select IRL mode for IRL3-0 + IRL7-4 */ in plat_irq_setup()
757 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
767 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); in plat_irq_setup_pins()
771 /* select IRQ mode for IRL3-0 */ in plat_irq_setup_pins()
772 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
777 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
778 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
782 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
783 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
787 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
792 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
814 if (irq > 0) { in sh7786_devices_setup()
829 if (unlikely(ret != 0)) in sh7786_devices_setup()