Lines Matching +full:0 +full:xfe920000
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
36 .id = 0,
51 DEFINE_RES_MEM(0xffe10000, 0x100),
52 DEFINE_RES_IRQ(evt2irq(0xc20)),
72 DEFINE_RES_MEM(0xffe20000, 0x100),
73 DEFINE_RES_IRQ(evt2irq(0xc40)),
92 DEFINE_RES_MEM(0xa4e30000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0x900)),
112 DEFINE_RES_MEM(0xa4e40000, 0x100),
113 DEFINE_RES_IRQ(evt2irq(0xd00)),
132 DEFINE_RES_MEM(0xa4e50000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0xfa0)),
148 .version = "0",
149 .irq = evt2irq(0x980),
153 [0] = {
155 .start = 0xfe900000,
156 .end = 0xfe902807,
166 .id = 0,
176 .version = "0",
177 .irq = evt2irq(0x8c0),
181 [0] = {
183 .start = 0xfe920000,
184 .end = 0xfe92027b,
204 .version = "0",
205 .irq = evt2irq(0x560),
209 [0] = {
211 .start = 0xfe924000,
212 .end = 0xfe92427b,
231 .channels_mask = 0x20,
235 DEFINE_RES_MEM(0x044a0000, 0x70),
236 DEFINE_RES_IRQ(evt2irq(0xf00)),
241 .id = 0,
254 DEFINE_RES_MEM(0xffd80000, 0x2c),
255 DEFINE_RES_IRQ(evt2irq(0x400)),
256 DEFINE_RES_IRQ(evt2irq(0x420)),
257 DEFINE_RES_IRQ(evt2irq(0x440)),
262 .id = 0,
275 DEFINE_RES_MEM(0xffd90000, 0x2c),
276 DEFINE_RES_IRQ(evt2irq(0x920)),
277 DEFINE_RES_IRQ(evt2irq(0x940)),
278 DEFINE_RES_IRQ(evt2irq(0x960)),
292 [0] = {
293 .start = 0xa465fec0,
294 .end = 0xa465fec0 + 0x58 - 1,
299 .start = evt2irq(0xaa0),
304 .start = evt2irq(0xac0),
309 .start = evt2irq(0xa80),
326 [0] = {
327 .start = 0xa4d80000,
328 .end = 0xa4d800ff,
332 .start = evt2irq(0xa20),
333 .end = evt2irq(0xa20),
340 .id = 0,
343 .coherent_dma_mask = 0xffffffff,
351 [0] = {
353 .start = 0x04470000,
354 .end = 0x04470017,
358 .start = evt2irq(0xe00),
359 .end = evt2irq(0xe60),
366 .id = 0, /* "i2c0" clock */
418 #define RAMCR_CACHE_L2FC 0x0002
419 #define RAMCR_CACHE_L2E 0x0001
429 UNUSED=0,
471 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
472 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
473 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
474 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
476 INTC_VECT(DMAC1A_DEI0,0x700),
477 INTC_VECT(DMAC1A_DEI1,0x720),
478 INTC_VECT(DMAC1A_DEI2,0x740),
479 INTC_VECT(DMAC1A_DEI3,0x760),
481 INTC_VECT(_2DG_TRI, 0x780),
482 INTC_VECT(_2DG_INI, 0x7A0),
483 INTC_VECT(_2DG_CEI, 0x7C0),
485 INTC_VECT(DMAC0A_DEI0,0x800),
486 INTC_VECT(DMAC0A_DEI1,0x820),
487 INTC_VECT(DMAC0A_DEI2,0x840),
488 INTC_VECT(DMAC0A_DEI3,0x860),
490 INTC_VECT(VIO_CEUI,0x880),
491 INTC_VECT(VIO_BEUI,0x8A0),
492 INTC_VECT(VIO_VEU2HI,0x8C0),
493 INTC_VECT(VIO_VOUI,0x8E0),
495 INTC_VECT(SCIFA_SCIFA0,0x900),
496 INTC_VECT(VPU_VPUI,0x980),
497 INTC_VECT(TPU_TPUI,0x9A0),
498 INTC_VECT(ADC_ADI,0x9E0),
499 INTC_VECT(USB_USI0,0xA20),
501 INTC_VECT(RTC_ATI,0xA80),
502 INTC_VECT(RTC_PRI,0xAA0),
503 INTC_VECT(RTC_CUI,0xAC0),
505 INTC_VECT(DMAC1B_DEI4,0xB00),
506 INTC_VECT(DMAC1B_DEI5,0xB20),
507 INTC_VECT(DMAC1B_DADERR,0xB40),
509 INTC_VECT(DMAC0B_DEI4,0xB80),
510 INTC_VECT(DMAC0B_DEI5,0xBA0),
511 INTC_VECT(DMAC0B_DADERR,0xBC0),
513 INTC_VECT(KEYSC_KEYI,0xBE0),
514 INTC_VECT(SCIF_SCIF0,0xC00),
515 INTC_VECT(SCIF_SCIF1,0xC20),
516 INTC_VECT(SCIF_SCIF2,0xC40),
517 INTC_VECT(MSIOF_MSIOFI0,0xC80),
518 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
519 INTC_VECT(SCIFA_SCIFA1,0xD00),
521 INTC_VECT(FLCTL_FLSTEI,0xD80),
522 INTC_VECT(FLCTL_FLTENDI,0xDA0),
523 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
524 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
526 INTC_VECT(I2C_ALI,0xE00),
527 INTC_VECT(I2C_TACKI,0xE20),
528 INTC_VECT(I2C_WAITI,0xE40),
529 INTC_VECT(I2C_DTEI,0xE60),
531 INTC_VECT(SDHI0, 0xE80),
532 INTC_VECT(SDHI0, 0xEA0),
533 INTC_VECT(SDHI0, 0xEC0),
535 INTC_VECT(CMT_CMTI,0xF00),
536 INTC_VECT(TSIF_TSIFI,0xF20),
537 INTC_VECT(SIU_SIUI,0xF80),
538 INTC_VECT(SCIFA_SCIFA2,0xFA0),
540 INTC_VECT(TMU0_TUNI0,0x400),
541 INTC_VECT(TMU0_TUNI1,0x420),
542 INTC_VECT(TMU0_TUNI2,0x440),
544 INTC_VECT(IRDA_IRDAI,0x480),
545 INTC_VECT(ATAPI_ATAPII,0x4A0),
547 INTC_VECT(SDHI1, 0x4E0),
548 INTC_VECT(SDHI1, 0x500),
549 INTC_VECT(SDHI1, 0x520),
551 INTC_VECT(VEU2H1_VEU2HI,0x560),
552 INTC_VECT(LCDC_LCDCI,0x580),
554 INTC_VECT(TMU1_TUNI0,0x920),
555 INTC_VECT(TMU1_TUNI1,0x940),
556 INTC_VECT(TMU1_TUNI2,0x960),
573 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
574 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
575 0, ENABLED, ENABLED, ENABLED } },
576 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
578 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
579 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
580 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
581 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
582 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
583 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
584 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
585 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
586 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
587 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
588 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
591 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
592 { 0, ENABLED, ENABLED, ENABLED,
593 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
594 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
595 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
596 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
597 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
598 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
599 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
600 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
601 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
602 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
607 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
608 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
609 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
610 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
611 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
612 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
613 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
614 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
615 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
616 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
617 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
618 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
619 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
624 { 0xa414001c, 16, 2, /* ICR1 */
629 { 0xa4140024, 0, 8, /* INTREQ00 */