Lines Matching +full:0 +full:x00500000

17 #define PA_ROM		0xa0000000	/* EPROM */
18 #define PA_ROM_SIZE	0x00200000	/* EPROM size 2M byte */
19 #define PA_FROM		0xa1000000	/* Flash-ROM */
20 #define PA_FROM_SIZE	0x01000000	/* Flash-ROM size 16M byte */
21 #define PA_EXT1		0xa4000000
22 #define PA_EXT1_SIZE	0x04000000
23 #define PA_SDRAM	0xaC000000	/* DDR-SDRAM(Area3) 64MB */
24 #define PA_SDRAM_SIZE	0x04000000
26 #define PA_EXT4		0xb0000000
27 #define PA_EXT4_SIZE	0x04000000
29 #define PA_PERIPHERAL	0xB0000000
32 #define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)    /* MR-SHPC-01 PCMCIA controller */
33 #define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)    /* MR-SHPC-01 memory window base */
34 #define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)    /* MR-SHPC-01 attribute window base */
35 #define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)    /* MR-SHPC-01 I/O window base */
50 #define PA_LED		(PA_PERIPHERAL + 0x00800000)	/* 8bit LED */
51 #define PA_FPGA		(PA_PERIPHERAL + 0x01800000)	/* FPGA base address */
53 #define PA_LAN		(PA_AREA6_IO + 0)		/* SMC LAN91C111 */
55 #define FPGA_IN         0xb1840000UL
56 #define FPGA_OUT        0xb1840004UL
58 #define PORT_PECR       0xA4050108UL
59 #define PORT_PJCR       0xA4050110UL
60 #define PORT_PSELD      0xA4050154UL
61 #define PORT_PSELB      0xA4050150UL
63 #define PORT_PSELC      0xA4050152UL
64 #define PORT_PKCR       0xA4050112UL
65 #define PORT_PHCR       0xA405010EUL
66 #define PORT_PLCR       0xA4050114UL
67 #define PORT_PMCR       0xA4050116UL
68 #define PORT_PRCR       0xA405011CUL
69 #define PORT_PXCR       0xA4050148UL
70 #define PORT_PSELA      0xA405014EUL
71 #define PORT_PYCR       0xA405014AUL
72 #define PORT_PZCR       0xA405014CUL
73 #define PORT_HIZCRA     0xA4050158UL
74 #define PORT_HIZCRC     0xA405015CUL
77 #define IRQ0_IRQ        evt2irq(0x600)
78 #define IRQ1_IRQ        evt2irq(0x620)
80 #define SE7722_FPGA_IRQ_USB	0 /* IRQ0 */