45 		.name	= "PCIe0 MEM 0",
46 		.start	= 0xfd000000,
47 		.end	= 0xfd000000 + SZ_8M - 1,
51 		.start	= 0xc0000000,
52 		.end	= 0xc0000000 + SZ_512M - 1,
56 		.start	= 0x10000000,
57 		.end	= 0x10000000 + SZ_64M - 1,
61 		.start	= 0xfe100000,
62 		.end	= 0xfe100000 + SZ_1M - 1,
69 		.name	= "PCIe1 MEM 0",
70 		.start	= 0xfd800000,
71 		.end	= 0xfd800000 + SZ_8M - 1,
75 		.start	= 0xa0000000,
76 		.end	= 0xa0000000 + SZ_512M - 1,
80 		.start	= 0x30000000,
81 		.end	= 0x30000000 + SZ_256M - 1,
85 		.start	= 0xfe300000,
86 		.end	= 0xfe300000 + SZ_1M - 1,
93 		.name	= "PCIe2 MEM 0",
94 		.start	= 0xfc800000,
95 		.end	= 0xfc800000 + SZ_4M - 1,
99 		.start	= 0x80000000,
100 		.end	= 0x80000000 + SZ_512M - 1,
104 		.start	= 0x20000000,
105 		.end	= 0x20000000 + SZ_256M - 1,
109 		.start	= 0xfcd00000,
110 		.end	= 0xfcd00000 + SZ_1M - 1,
123 	.mem_offset	= 0,						\
124 	.io_offset	= 0,						\
128 	DEFINE_CONTROLLER(0xfe000000, 0),
129 	DEFINE_CONTROLLER(0xfe200000, 1),
130 	DEFINE_CONTROLLER(0xfcc00000, 2),
142 	if (pci_is_root_bus(dev->bus) && dev->devfn == 0) {  in sh7786_pci_fixup()
145 		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {  in sh7786_pci_fixup()
146 			dev->resource[i].start	= 0;  in sh7786_pci_fixup()
147 			dev->resource[i].end	= 0;  in sh7786_pci_fixup()
148 			dev->resource[i].flags	= 0;  in sh7786_pci_fixup()
161 			return 0;  in phy_wait_for_ack()
175 			return 0;  in pci_wait_for_irq()
188 	phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +  in phy_write_reg()
189 			((addr & 0xff) << BITS_ADR);  in phy_write_reg()
198 	pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);  in phy_write_reg()
199 	pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);  in phy_write_reg()
215 	if (unlikely(ret != 0))  in pcie_clk_init()
238 	memset(clk, 0, sizeof(struct clk));  in pcie_clk_init()
245 	if (unlikely(ret < 0))  in pcie_clk_init()
248 	return 0;  in pcie_clk_init()
267 	phy_write_reg(chan, 0x60, 0xf, 0x004b008b);  in phy_init()
268 	phy_write_reg(chan, 0x61, 0xf, 0x00007b41);  in phy_init()
269 	phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);  in phy_init()
270 	phy_write_reg(chan, 0x65, 0xf, 0x09070907);  in phy_init()
271 	phy_write_reg(chan, 0x66, 0xf, 0x00000010);  in phy_init()
272 	phy_write_reg(chan, 0x74, 0xf, 0x0007001c);  in phy_init()
273 	phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);  in phy_init()
274 	phy_write_reg(chan, 0xb0, 0xf, 0x00000610);  in phy_init()
277 	phy_write_reg(chan, 0x67, 0x1, 0x00000400);  in phy_init()
284 			return 0;  in phy_init()
297 	pci_write_reg(chan, 0, SH4A_PCIETCTLR);  in pcie_reset()
298 	pci_write_reg(chan, 0, SH4A_PCIESRSTR);  in pcie_reset()
299 	pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);  in pcie_reset()
348 	data &= ~0x3f00;  in pcie_init()
349 	data |= 0x32 << 8;  in pcie_init()
358 	data |= (0xff << 16);  in pcie_init()
386 		pci_write_reg(chan, 0, SH4A_PCIELAR1);  in pcie_init()
387 		pci_write_reg(chan, 0, SH4A_PCIELAMR1);  in pcie_init()
399 	data |= 0x1;  in pcie_init()
412 	data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);  in pcie_init()
428 	pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);  in pcie_init()
429 	pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);  in pcie_init()
433 	if (ret == 0) {  in pcie_init()
436 		       port->index, (data >> 20) & 0x3f);  in pcie_init()
441 	for (i = win = 0; i < chan->nr_resources; i++) {  in pcie_init()
456 		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));  in pcie_init()
480 	return 0;  in pcie_init()
485         return evt2irq(0xae0);  in pcibios_map_platform_irq()
515 	if (unlikely(ret < 0)) {  in sh7786_pcie_init_hw()
522 	if (unlikely(ret < 0)) {  in sh7786_pcie_init_hw()
529 	if (unlikely(ret < 0)) {  in sh7786_pcie_init_hw()
559 	if (unlikely(nr_ports == 0))  in sh7786_pcie_init()
595 	for (i = 0; i < nr_ports; i++) {  in sh7786_pcie_init()
600 		port->hose->io_map_base	= port->hose->resources[0].start;  in sh7786_pcie_init()
607 	return 0;  in sh7786_pcie_init()