22 	RV_REG_ZERO =	0,	/* The constant value 0 */
92 	memset(area, 0, size);  in bpf_fill_ill_insns()
199 	return 0;  in is_12b_check()
217 	from = (insn > 0) ? ctx->offset[insn - 1] : 0;  in rv_offset()
218 	to = (insn + off > 0) ? ctx->offset[insn + off - 1] : 0;  in rv_offset()
239 	u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f;  in rv_s_insn()
247 	u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4);  in rv_b_insn()
248 	u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10);  in rv_b_insn()
263 	imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) |  in rv_j_insn()
264 		((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11);  in rv_j_insn()
288 	imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);  in rv_ci_insn()
299 	return (funct3 << 13) | (uimm << 5) | ((rd & 0x7) << 2) | op;  in rv_ciw_insn()
305 	return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |  in rv_cl_insn()
306 		(imm_lo << 5) | ((rd & 0x7) << 2) | op;  in rv_cl_insn()
312 	return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |  in rv_cs_insn()
313 		(imm_lo << 5) | ((rs2 & 0x7) << 2) | op;  in rv_cs_insn()
318 	return (funct6 << 10) | ((rd & 0x7) << 7) | (funct2 << 5) |  in rv_ca_insn()
319 		((rs2 & 0x7) << 2) | op;  in rv_ca_insn()
326 	imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);  in rv_cb_insn()
327 	return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm;  in rv_cb_insn()
334 	return rv_i_insn(imm11_0, rs1, 0, rd, 0x13);  in rv_addi()
339 	return rv_i_insn(imm11_0, rs1, 7, rd, 0x13);  in rv_andi()
344 	return rv_i_insn(imm11_0, rs1, 6, rd, 0x13);  in rv_ori()
349 	return rv_i_insn(imm11_0, rs1, 4, rd, 0x13);  in rv_xori()
354 	return rv_i_insn(imm11_0, rs1, 1, rd, 0x13);  in rv_slli()
359 	return rv_i_insn(imm11_0, rs1, 5, rd, 0x13);  in rv_srli()
364 	return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13);  in rv_srai()
369 	return rv_u_insn(imm31_12, rd, 0x37);  in rv_lui()
374 	return rv_u_insn(imm31_12, rd, 0x17);  in rv_auipc()
379 	return rv_r_insn(0, rs2, rs1, 0, rd, 0x33);  in rv_add()
384 	return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33);  in rv_sub()
389 	return rv_r_insn(0, rs2, rs1, 3, rd, 0x33);  in rv_sltu()
394 	return rv_r_insn(0, rs2, rs1, 7, rd, 0x33);  in rv_and()
399 	return rv_r_insn(0, rs2, rs1, 6, rd, 0x33);  in rv_or()
404 	return rv_r_insn(0, rs2, rs1, 4, rd, 0x33);  in rv_xor()
409 	return rv_r_insn(0, rs2, rs1, 1, rd, 0x33);  in rv_sll()
414 	return rv_r_insn(0, rs2, rs1, 5, rd, 0x33);  in rv_srl()
419 	return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33);  in rv_sra()
424 	return rv_r_insn(1, rs2, rs1, 0, rd, 0x33);  in rv_mul()
429 	return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);  in rv_mulhu()
434 	return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);  in rv_divu()
439 	return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);  in rv_remu()
444 	return rv_j_insn(imm20_1, rd, 0x6f);  in rv_jal()
449 	return rv_i_insn(imm11_0, rs1, 0, rd, 0x67);  in rv_jalr()
454 	return rv_b_insn(imm12_1, rs2, rs1, 0, 0x63);  in rv_beq()
459 	return rv_b_insn(imm12_1, rs2, rs1, 1, 0x63);  in rv_bne()
464 	return rv_b_insn(imm12_1, rs2, rs1, 6, 0x63);  in rv_bltu()
474 	return rv_b_insn(imm12_1, rs2, rs1, 7, 0x63);  in rv_bgeu()
484 	return rv_b_insn(imm12_1, rs2, rs1, 4, 0x63);  in rv_blt()
494 	return rv_b_insn(imm12_1, rs2, rs1, 5, 0x63);  in rv_bge()
504 	return rv_i_insn(imm11_0, rs1, 2, rd, 0x03);  in rv_lw()
509 	return rv_i_insn(imm11_0, rs1, 4, rd, 0x03);  in rv_lbu()
514 	return rv_i_insn(imm11_0, rs1, 5, rd, 0x03);  in rv_lhu()
519 	return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23);  in rv_sb()
524 	return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23);  in rv_sh()
529 	return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23);  in rv_sw()
534 	return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f);  in rv_amoadd_w()
543 	imm = ((imm10 & 0x30) << 2) | ((imm10 & 0x3c0) >> 4) |  in rvc_addi4spn()
544 		((imm10 & 0x4) >> 1) | ((imm10 & 0x8) >> 3);  in rvc_addi4spn()
545 	return rv_ciw_insn(0x0, imm, rd, 0x0);  in rvc_addi4spn()
552 	imm_hi = (imm7 & 0x38) >> 3;  in rvc_lw()
553 	imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);  in rvc_lw()
554 	return rv_cl_insn(0x2, imm_hi, rs1, imm_lo, rd, 0x0);  in rvc_lw()
561 	imm_hi = (imm7 & 0x38) >> 3;  in rvc_sw()
562 	imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);  in rvc_sw()
563 	return rv_cs_insn(0x6, imm_hi, rs1, imm_lo, rs2, 0x0);  in rvc_sw()
568 	return rv_ci_insn(0, imm6, rd, 0x1);  in rvc_addi()
573 	return rv_ci_insn(0x2, imm6, rd, 0x1);  in rvc_li()
580 	imm = ((imm10 & 0x200) >> 4) | (imm10 & 0x10) | ((imm10 & 0x40) >> 3) |  in rvc_addi16sp()
581 		((imm10 & 0x180) >> 6) | ((imm10 & 0x20) >> 5);  in rvc_addi16sp()
582 	return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1);  in rvc_addi16sp()
587 	return rv_ci_insn(0x3, imm6, rd, 0x1);  in rvc_lui()
592 	return rv_cb_insn(0x4, imm6, 0, rd, 0x1);  in rvc_srli()
597 	return rv_cb_insn(0x4, imm6, 0x1, rd, 0x1);  in rvc_srai()
602 	return rv_cb_insn(0x4, imm6, 0x2, rd, 0x1);  in rvc_andi()
607 	return rv_ca_insn(0x23, rd, 0, rs, 0x1);  in rvc_sub()
612 	return rv_ca_insn(0x23, rd, 0x1, rs, 0x1);  in rvc_xor()
617 	return rv_ca_insn(0x23, rd, 0x2, rs, 0x1);  in rvc_or()
622 	return rv_ca_insn(0x23, rd, 0x3, rs, 0x1);  in rvc_and()
627 	return rv_ci_insn(0, imm6, rd, 0x2);  in rvc_slli()
634 	imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c);  in rvc_lwsp()
635 	return rv_ci_insn(0x2, imm, rd, 0x2);  in rvc_lwsp()
640 	return rv_cr_insn(0x8, rs1, RV_REG_ZERO, 0x2);  in rvc_jr()
645 	return rv_cr_insn(0x8, rd, rs, 0x2);  in rvc_mv()
650 	return rv_cr_insn(0x9, rs1, RV_REG_ZERO, 0x2);  in rvc_jalr()
655 	return rv_cr_insn(0x9, rd, rs, 0x2);  in rvc_add()
662 	imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6);  in rvc_swsp()
663 	return rv_css_insn(0x6, imm, rs2, 0x2);  in rvc_swsp()
677 	return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b);  in rv_addiw()
682 	return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b);  in rv_slliw()
687 	return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b);  in rv_srliw()
692 	return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b);  in rv_sraiw()
697 	return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b);  in rv_addw()
702 	return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b);  in rv_subw()
707 	return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b);  in rv_sllw()
712 	return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b);  in rv_srlw()
717 	return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b);  in rv_sraw()
722 	return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);  in rv_mulw()
727 	return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);  in rv_divuw()
732 	return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);  in rv_remuw()
737 	return rv_i_insn(imm11_0, rs1, 3, rd, 0x03);  in rv_ld()
742 	return rv_i_insn(imm11_0, rs1, 6, rd, 0x03);  in rv_lwu()
747 	return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23);  in rv_sd()
752 	return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f);  in rv_amoadd_d()
761 	imm_hi = (imm8 & 0x38) >> 3;  in rvc_ld()
762 	imm_lo = (imm8 & 0xc0) >> 6;  in rvc_ld()
763 	return rv_cl_insn(0x3, imm_hi, rs1, imm_lo, rd, 0x0);  in rvc_ld()
770 	imm_hi = (imm8 & 0x38) >> 3;  in rvc_sd()
771 	imm_lo = (imm8 & 0xc0) >> 6;  in rvc_sd()
772 	return rv_cs_insn(0x7, imm_hi, rs1, imm_lo, rs2, 0x0);  in rvc_sd()
777 	return rv_ca_insn(0x27, rd, 0, rs, 0x1);  in rvc_subw()
782 	return rv_ci_insn(0x1, imm6, rd, 0x1);  in rvc_addiw()
789 	imm = ((imm9 & 0x1c0) >> 6) | (imm9 & 0x38);  in rvc_ldsp()
790 	return rv_ci_insn(0x3, imm, rd, 0x2);  in rvc_ldsp()
797 	imm = (imm9 & 0x38) | ((imm9 & 0x1c0) >> 6);  in rvc_sdsp()
798 	return rv_css_insn(0x7, imm, rs2, 0x2);  in rvc_sdsp()
820 		emit(rv_addi(rd, rs, 0), ctx);  in emit_mv()
833 	if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf))  in emit_addi()
836 		 !(imm & 0x3) && imm)  in emit_addi()
926 	if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3))  in emit_lw()
928 	else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_7b_uint(off) && !(off & 0x3))  in emit_lw()
936 	if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3))  in emit_sw()
938 	else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_7b_uint(off) && !(off & 0x3))  in emit_sw()
957 	if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7))  in emit_ld()
959 	else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_8b_uint(off) && !(off & 0x7))  in emit_ld()
967 	if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7))  in emit_sd()
969 	else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_8b_uint(off) && !(off & 0x7))  in emit_sd()