Lines Matching refs:SH_RD
97 #define SH_RD 7 macro
118 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
142 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
275 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
277 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
284 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
286 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_load()
292 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
300 insn = RVC_RS2S(insn) << SH_RD; in handle_misaligned_load()
348 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_store()
356 ((insn >> SH_RD) & 0x1f)) { in handle_misaligned_store()