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3 Written by Ian Lance Taylor, Cygnus Support
9 License as published by the Free Software Foundation; either version
41 /* The opcode mask. This is used by the disassembler. This is a
44 match (and are presumably filled in by operands). */
59 appear in assembly code, and are terminated by a zero. */
63 /* The table itself is sorted by major opcode number, and is otherwise
82 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
104 /* Opcode is supported by Altivec Vector Unit */
107 /* Opcode is supported by PowerPC 403 processor. */
110 /* Opcode is supported by PowerPC BookE processor. */
113 /* Opcode is supported by PowerPC 440 processor. */
116 /* Opcode is only supported by Power4 architecture. */
119 /* Opcode is only supported by Power7 architecture. */
122 /* Opcode is only supported by e500x2 Core. */
125 /* Opcode is supported by e500x2 Integer select APU. */
131 /* Opcode is supported by branch locking APU. */
134 /* Opcode is supported by performance monitor APU. */
137 /* Opcode is supported by cache locking APU. */
140 /* Opcode is supported by machine check APU. */
143 /* Opcode is only supported by Power5 architecture. */
146 /* Opcode is supported by PowerPC e300 family. */
149 /* Opcode is only supported by Power6 architecture. */
152 /* Opcode is only supported by PowerPC Cell family. */
155 /* Opcode is supported by CPUs with paired singles support. */
158 /* Opcode is supported by Power E500MC */
161 /* Opcode is supported by PowerPC 405 processor. */
164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
167 /* Opcode is supported by A2. */
170 /* Opcode is supported by PowerPC 476 processor. */
173 /* Opcode is supported by AppliedMicro Titan core */
176 /* Opcode which is supported by the e500 family */
179 /* Opcode is supported by Extended Altivec Vector Unit */
182 /* Opcode is supported by Power E6500 */
185 /* Opcode is supported by Thread management APU */
188 /* Opcode which is supported by the VLE extension. */
191 /* Opcode is only supported by Power8 architecture. */
194 /* Opcode which is supported by the Hardware Transactional Memory extension. */
199 /* Opcode is supported by ppc750cl. */
202 /* Opcode is supported by ppc7450. */
205 /* Opcode is supported by ppc821/850/860. */
208 /* Opcode is only supported by Power9 architecture. */
211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
214 /* Opcode is supported by e200z4. */
238 is shifted left by SHIFT. For negative values, the operand
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
244 /* Insertion function. This is used by the assembler. To insert an
265 /* Extraction function. This is used by the disassembler. To
290 /* Elements in the table are retrieved by indexing with values from
321 separated from this one by a comma. This is used for the load and