1 // SPDX-License-Identifier: GPL-2.0-only
28  * enum spe_type - Type of spe to create.
40  * struct spe_shadow - logical spe shadow register area.
42  * Read-only shadow of spe registers.
50 	u8 padding_0158[0x0610-0x0158];
52 	u8 padding_0618[0x0620-0x0618];
54 	u8 padding_0628[0x0800-0x0628];
56 	u8 padding_0808[0x0810-0x0808];
58 	u8 padding_0818[0x0c00-0x0818];
60 	u8 padding_0c08[0x0f00-0x0c08];
62 	u8 padding_0f08[0x1000-0x0f08];
66  * enum spe_ex_state - Logical spe execution state.
82  * struct priv1_cache - Cached values of priv1 registers.
95  * struct spu_pdata - Platform state variables.
118 	return spu->pdata;  in spu_pdata()
136 	return spu_pdata(arg)->spe_id;  in ps3_get_spe_id()
159 		&spu_pdata(spu)->priv2_addr, &problem_phys,  in construct_spu()
161 		&spu_pdata(spu)->shadow_addr,  in construct_spu()
162 		&spu_pdata(spu)->spe_id);  in construct_spu()
163 	spu->problem_phys = problem_phys;  in construct_spu()
164 	spu->local_store_phys = local_store_phys;  in construct_spu()
177 	iounmap(spu->priv2);  in spu_unmap()
178 	iounmap(spu->problem);  in spu_unmap()
179 	iounmap((__force u8 __iomem *)spu->local_store);  in spu_unmap()
180 	iounmap(spu_pdata(spu)->shadow);  in spu_unmap()
184  * setup_areas - Map the spu regions into the address space.
187  * PTE page protection bits set as read-only.
195 	spu_pdata(spu)->shadow = ioremap_prot(spu_pdata(spu)->shadow_addr,  in setup_areas()
197 	if (!spu_pdata(spu)->shadow) {  in setup_areas()
202 	spu->local_store = (__force void *)ioremap_wc(spu->local_store_phys, LS_SIZE);  in setup_areas()
204 	if (!spu->local_store) {  in setup_areas()
210 	spu->problem = ioremap(spu->problem_phys,  in setup_areas()
213 	if (!spu->problem) {  in setup_areas()
218 	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,  in setup_areas()
221 	if (!spu->priv2) {  in setup_areas()
226 	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,  in setup_areas()
227 		spu->problem_phys, spu->local_store_phys,  in setup_areas()
228 		spu_pdata(spu)->shadow_addr);  in setup_areas()
229 	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,  in setup_areas()
230 		(unsigned long)spu->problem, (unsigned long)spu->local_store,  in setup_areas()
231 		(unsigned long)spu_pdata(spu)->shadow);  in setup_areas()
238 	return -ENOMEM;  in setup_areas()
245 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
246 		0, &spu->irqs[0]);  in setup_interrupts()
251 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
252 		1, &spu->irqs[1]);  in setup_interrupts()
257 	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,  in setup_interrupts()
258 		2, &spu->irqs[2]);  in setup_interrupts()
266 	ps3_spe_irq_destroy(spu->irqs[1]);  in setup_interrupts()
268 	ps3_spe_irq_destroy(spu->irqs[0]);  in setup_interrupts()
270 	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;  in setup_interrupts()
278 	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,  in enable_spu()
279 		spu_pdata(spu)->resource_id);  in enable_spu()
302 	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);  in enable_spu()
311 	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);  in ps3_destroy_spu()
313 	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);  in ps3_destroy_spu()
316 	ps3_spe_irq_destroy(spu->irqs[2]);  in ps3_destroy_spu()
317 	ps3_spe_irq_destroy(spu->irqs[1]);  in ps3_destroy_spu()
318 	ps3_spe_irq_destroy(spu->irqs[0]);  in ps3_destroy_spu()
320 	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;  in ps3_destroy_spu()
324 	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);  in ps3_destroy_spu()
327 	kfree(spu->pdata);  in ps3_destroy_spu()
328 	spu->pdata = NULL;  in ps3_destroy_spu()
337 	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);  in ps3_create_spu()
339 	spu->pdata = kzalloc(sizeof(struct spu_pdata),  in ps3_create_spu()
342 	if (!spu->pdata) {  in ps3_create_spu()
343 		result = -ENOMEM;  in ps3_create_spu()
347 	spu_pdata(spu)->resource_id = (unsigned long)data;  in ps3_create_spu()
351 	spu_pdata(spu)->cache.sr1 = 0x33;  in ps3_create_spu()
368 	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)  in ps3_create_spu()
394 	 * of physical spus reserved for the partition.  in ps3_enumerate_spus()
430  * ps3_enable_spu - Enable SPU run control.
448 	ctx->ops->runcntl_stop(ctx);  in ps3_disable_spu()
481 	spu_pdata(spu)->cache.masks[class] = mask;  in int_mask_set()
482 	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,  in int_mask_set()
483 		spu_pdata(spu)->cache.masks[class]);  in int_mask_set()
488 	return spu_pdata(spu)->cache.masks[class];  in int_mask_get()
495 	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,  in int_stat_clear()
503 	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);  in int_stat_get()
514 	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);  in mfc_dar_get()
524 	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);  in mfc_dsisr_get()
539 	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));  in mfc_sr1_set()
541 	spu_pdata(spu)->cache.sr1 = sr1;  in mfc_sr1_set()
543 		spu_pdata(spu)->spe_id,  in mfc_sr1_set()
545 		spu_pdata(spu)->cache.sr1);  in mfc_sr1_set()
550 	return spu_pdata(spu)->cache.sr1;  in mfc_sr1_get()
555 	spu_pdata(spu)->cache.tclass_id = tclass_id;  in mfc_tclass_id_set()
557 		spu_pdata(spu)->spe_id,  in mfc_tclass_id_set()
559 		spu_pdata(spu)->cache.tclass_id);  in mfc_tclass_id_set()
564 	return spu_pdata(spu)->cache.tclass_id;  in mfc_tclass_id_get()