56 #define BANDIT_MAGIC	0x50
57 #define BANDIT_COHERENT	0x40
126 	| (((unsigned int)(off)) & 0xFCUL))
131 	|(((unsigned int)(off)) & 0xFCUL) \
157 	offset &= has_uninorth ? 0x07 : 0x03;  in macrisc_cfg_map_bus()
178 	if (offset >= 0x100)  in chaos_map_bus()
189 	if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)  in chaos_map_bus()
190 	    && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))  in chaos_map_bus()
208 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_chaos()
209 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_chaos()
222  *  0 -> No special case
224  *       (return 0xff's on reads, eventually, cache config space
241 	else if (devfn == 0)  in u3_ht_skip_device()
242 		return 0;  in u3_ht_skip_device()
255 	for (i=0; i<2; i++)  in u3_ht_skip_device()
259 	return 0;  in u3_ht_skip_device()
267 		+ 0x01000000UL)
274 		if (devfn != 0)  in u3_ht_cfg_access()
276 		*swap = 0;  in u3_ht_cfg_access()
292 	if (offset >= 0x100)  in u3_ht_read_config()
299 	case 0:  in u3_ht_read_config()
304 			*val = 0xff; break;  in u3_ht_read_config()
306 			*val = 0xffff; break;  in u3_ht_read_config()
308 			*val = 0xfffffffful; break;  in u3_ht_read_config()
343 	if (offset >= 0x100)  in u3_ht_write_config()
350 	case 0:  in u3_ht_write_config()
386 	 | (((unsigned int)(off)) & 0xfcU))
392 	 |(((unsigned int)(off)) & 0xfcU)	\
402 	if (offset >= 0x1000)  in u4_pcie_cfg_map_bus()
419 	offset &= 0x03;  in u4_pcie_cfg_map_bus()
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
456 	/* read the word at offset 0 in config space for device 11 */  in init_bandit()
475 	/* read the word at offset 0x50 */  in init_bandit()
479 	if ((magic & BANDIT_COHERENT) != 0)  in init_bandit()
502 	if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {  in init_p2pbridge()
515 				   PCI_BRIDGE_CONTROL, &val) < 0) {  in init_p2pbridge()
538 	if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {  in init_second_ohare()
574 		if (0x1033 != *prop)  in fixup_nec_usb2()
579 		if (0x0035 != *prop)  in fixup_nec_usb2()
584 		devfn = (prop[0] >> 8) & 0xff;  in fixup_nec_usb2()
585 		bus = (prop[0] >> 16) & 0xff;  in fixup_nec_usb2()
586 		if (PCI_FUNC(devfn) != 0)  in fixup_nec_usb2()
591 		early_read_config_dword(hose, bus, devfn, 0xe4, &data);  in fixup_nec_usb2()
596 			early_write_config_dword(hose, bus, devfn, 0xe4, data);  in fixup_nec_usb2()
605 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_bandit()
606 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_bandit()
616 	hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);  in setup_uninorth()
617 	hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);  in setup_uninorth()
619 	return addr->start == 0xf2000000;  in setup_uninorth()
635 	hose->first_busno = 0xf0;  in setup_u3_agp()
636 	hose->last_busno = 0xff;  in setup_u3_agp()
639 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u3_agp()
640 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u3_agp()
650 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u4_pcie()
651 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u4_pcie()
654 	 * make it visible on bus 0 so that we pick the right type  in setup_u4_pcie()
659 	hose->first_busno = 0x00;  in setup_u4_pcie()
660 	hose->last_busno = 0xff;  in setup_u4_pcie()
672 	for (i = 0; i < 31; i++) {  in parse_region_decode()
673 		if ((decode & (0x80000000 >> i)) == 0)  in parse_region_decode()
676 			base = 0xf0000000 | (((u32)i) << 24);  in parse_region_decode()
677 			end = base + 0x00ffffff;  in parse_region_decode()
680 			end = base + 0x0fffffff;  in parse_region_decode()
691 			hose->mem_offset[cur] = 0;  in parse_region_decode()
692 			DBG("  %d: 0x%08lx-0x%08lx\n", cur, base, end);  in parse_region_decode()
694 			DBG("   :           -0x%08lx\n", end);  in parse_region_decode()
711 	if (of_address_to_resource(np, 0, &cfg_res) ||  in setup_u3_ht()
720 	hose->cfg_data = ioremap(cfg_res.start, 0x02000000);  in setup_u3_ht()
728 	hose->io_base_phys = 0xf4000000;  in setup_u3_ht()
729 	hose->pci_io_size = 0x00400000;  in setup_u3_ht()
731 	hose->io_resource.start = 0;  in setup_u3_ht()
732 	hose->io_resource.end = 0x003fffff;  in setup_u3_ht()
734 	hose->first_busno = 0;  in setup_u3_ht()
735 	hose->last_busno = 0xef;  in setup_u3_ht()
738 	decode = in_be32(hose->cfg_addr + 0x80);  in setup_u3_ht()
740 	DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);  in setup_u3_ht()
743 	 * 0xf8000000 for example is marked as enabled in there while it's  in setup_u3_ht()
747 	 * In a similar vein, region 0xf4000000 is actually the HT IO space but  in setup_u3_ht()
748 	 * also marked as enabled in here and 0xf9000000 is used by some other  in setup_u3_ht()
756 	 * Apple firmware doesn't assign things below 0xfa000000 for that  in setup_u3_ht()
759 	decode &= 0x003fffff;  in setup_u3_ht()
783 	of_address_to_resource(dev, 0, &rsrc);  in pmac_add_bridge()
789 		       " bus 0\n", dev);  in pmac_add_bridge()
795 	hose->first_busno = bus_range ? bus_range[0] : 0;  in pmac_add_bridge()
796 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in pmac_add_bridge()
806 		primary = 0;  in pmac_add_bridge()
814 		primary = 0;  in pmac_add_bridge()
835 		primary = 0;  in pmac_add_bridge()
837 	printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "  in pmac_add_bridge()
843 	DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",  in pmac_add_bridge()
853 	return 0;  in pmac_add_bridge()
882 		return 0;  in pmac_pci_root_bridge_prepare()
890 	PCI_DN(np)->busno = 0xf0;  in pmac_pci_root_bridge_prepare()
892 		PCI_DN(child)->busno = 0xf0;  in pmac_pci_root_bridge_prepare()
894 	return 0;  in pmac_pci_root_bridge_prepare()
915 			if (pmac_add_bridge(np) == 0)  in pmac_pci_init()
929 	if (ht && pmac_add_bridge(ht) != 0)  in pmac_pci_init()
945 		pcibios_assign_bus_offset = 0x10;  in pmac_pci_init()
953 	int updatecfg = 0;  in pmac_pci_enable_device_hook()
982 		pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);  in pmac_pci_enable_device_hook()
983 		pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);  in pmac_pci_enable_device_hook()
988 		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);  in pmac_pci_enable_device_hook()
1022 		dev->resource[0].flags = 0;  in pmac_pci_fixup_ohci()
1038 			pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);  in pmac_pcibios_after_init()
1039 			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);  in pmac_pcibios_after_init()
1045 			pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);  in pmac_pcibios_after_init()
1063 		if (pci_read_config_byte(dev, 0x91, &val) == 0)  in pmac_pci_fixup_cardbus()
1064 			pci_write_config_byte(dev, 0x91, val | 0x30);  in pmac_pci_fixup_cardbus()
1066 		if (pci_read_config_byte(dev, 0x92, &val) == 0)  in pmac_pci_fixup_cardbus()
1067 			pci_write_config_byte(dev, 0x92, val & ~0x06);  in pmac_pci_fixup_cardbus()
1074 		/* 0x8c == TI122X_IRQMUX, 2 says to route the INTA  in pmac_pci_fixup_cardbus()
1076 		if (pci_read_config_byte(dev, 0x8c, &val) == 0)  in pmac_pci_fixup_cardbus()
1077 			pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);  in pmac_pci_fixup_cardbus()
1079 		if (pci_read_config_byte(dev, 0x92, &val) == 0)  in pmac_pci_fixup_cardbus()
1080 			pci_write_config_byte(dev, 0x92, val & ~0x06);  in pmac_pci_fixup_cardbus()
1088        u8 progif = 0;  in pmac_pci_fixup_pciata()
1128 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);  in pmac_pci_fixup_pciata()
1129 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);  in pmac_pci_fixup_pciata()
1130 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);  in pmac_pci_fixup_pciata()
1131 			pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);  in pmac_pci_fixup_pciata()
1147 	if (PCI_FUNC(dev->devfn) > 0) {  in fixup_k2_sata()
1151 		for (i = 0; i < 6; i++) {  in fixup_k2_sata()
1152 			dev->resource[i].start = dev->resource[i].end = 0;  in fixup_k2_sata()
1153 			dev->resource[i].flags = 0;  in fixup_k2_sata()
1155 					       0);  in fixup_k2_sata()
1161 		for (i = 0; i < 5; i++) {  in fixup_k2_sata()
1162 			dev->resource[i].start = dev->resource[i].end = 0;  in fixup_k2_sata()
1163 			dev->resource[i].flags = 0;  in fixup_k2_sata()
1165 					       0);  in fixup_k2_sata()
1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1185  * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1201 	for (i = 0; i < 3; i++) {  in fixup_u4_pcie()
1205 		/* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they  in fixup_u4_pcie()
1208 		if (r->start >= 0xf0000000 && r->start < 0xf3000000)  in fixup_u4_pcie()
1224 	reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);  in fixup_u4_pcie()
1226 	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);  in fixup_u4_pcie()
1227 	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);  in fixup_u4_pcie()
1228 	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);  in fixup_u4_pcie()