Lines Matching full:event
9 * Power9 event codes.
11 EVENT(PM_CYC, 0x0001e)
12 EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
13 EVENT(PM_CMPLU_STALL, 0x1e054)
14 EVENT(PM_INST_CMPL, 0x00002)
15 EVENT(PM_BR_CMPL, 0x4d05e)
16 EVENT(PM_BR_MPRED_CMPL, 0x400f6)
19 EVENT(PM_LD_REF_L1, 0x100fc)
21 EVENT(PM_LD_MISS_L1_FIN, 0x2c04e)
22 EVENT(PM_LD_MISS_L1, 0x3e054)
23 /* Alternate event code for PM_LD_MISS_L1 */
24 EVENT(PM_LD_MISS_L1_ALT, 0x400f0)
26 EVENT(PM_ST_MISS_L1, 0x300f0)
28 EVENT(PM_L1_PREF, 0x20054)
30 EVENT(PM_INST_FROM_L1, 0x04080)
32 EVENT(PM_L1_ICACHE_MISS, 0x200fd)
34 EVENT(PM_L1_DEMAND_WRITE, 0x0408c)
36 EVENT(PM_IC_PREF_WRITE, 0x0488c)
38 EVENT(PM_DATA_FROM_L3, 0x4c042)
40 EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
42 EVENT(PM_L2_ST, 0x16880)
44 EVENT(PM_L2_ST_MISS, 0x26880)
46 EVENT(PM_L3_PREF_ALL, 0x4e052)
48 EVENT(PM_DTLB_MISS, 0x300fc)
50 EVENT(PM_ITLB_MISS, 0x400fc)
52 EVENT(PM_RUN_INST_CMPL, 0x500fa)
53 /* Alternate event code for PM_RUN_INST_CMPL */
54 EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa)
56 EVENT(PM_RUN_CYC, 0x600f4)
57 /* Alternate event code for Run_cycles */
58 EVENT(PM_RUN_CYC_ALT, 0x200f4)
60 EVENT(PM_INST_DISP, 0x200f2)
61 EVENT(PM_INST_DISP_ALT, 0x300f2)
62 /* Branch event that are not strongly biased */
63 EVENT(PM_BR_2PATH, 0x20036)
64 /* ALternate branch event that are not strongly biased */
65 EVENT(PM_BR_2PATH_ALT, 0x40036)
68 EVENT(PM_MRK_ST_DONE_L2, 0x10134)
69 EVENT(PM_RADIX_PWC_L1_HIT, 0x1f056)
70 EVENT(PM_FLOP_CMPL, 0x100f4)
71 EVENT(PM_MRK_NTF_FIN, 0x20112)
72 EVENT(PM_RADIX_PWC_L2_HIT, 0x2d024)
73 EVENT(PM_IFETCH_THROTTLE, 0x3405e)
74 EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER, 0x3e15c)
75 EVENT(PM_RADIX_PWC_L3_HIT, 0x3f056)
76 EVENT(PM_RUN_CYC_SMT2_MODE, 0x3006c)
77 EVENT(PM_TM_TX_PASS_RUN_INST, 0x4e014)
78 EVENT(PM_DISP_HELD_SYNC_HOLD, 0x4003c)
79 EVENT(PM_DTLB_MISS_16G, 0x1c058)
80 EVENT(PM_DERAT_MISS_2M, 0x1c05a)
81 EVENT(PM_DTLB_MISS_2M, 0x1c05c)
82 EVENT(PM_MRK_DTLB_MISS_1G, 0x1d15c)
83 EVENT(PM_DTLB_MISS_4K, 0x2c056)
84 EVENT(PM_DERAT_MISS_1G, 0x2c05a)
85 EVENT(PM_MRK_DERAT_MISS_2M, 0x2d152)
86 EVENT(PM_MRK_DTLB_MISS_4K, 0x2d156)
87 EVENT(PM_MRK_DTLB_MISS_16G, 0x2d15e)
88 EVENT(PM_DTLB_MISS_64K, 0x3c056)
89 EVENT(PM_MRK_DERAT_MISS_1G, 0x3d152)
90 EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156)
91 EVENT(PM_DTLB_MISS_16M, 0x4c056)
92 EVENT(PM_DTLB_MISS_1G, 0x4c05a)
93 EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e)
98 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
100 * needs to be programmed and corresponding raw event format
106 * TECE (Threshold Event Counter Event)
107 * TS (Threshold Start Event)
108 * TE (Threshold End Event)
116 EVENT(MEM_LOADS, 0x34340401e0)
117 EVENT(MEM_STORES, 0x343c0401e0)