38 #define EVENT_PMC_SHIFT		16	/* PMC number (1-based) */
130  *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
135  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
179  * For the per-PMC fields we have two bits. The low bit is added, so if two
180  * events ask for the same PMC the sum will overflow, setting the high bit,
183 #define CNST_PMC_SHIFT(pmc)	((pmc - 1) * 2)  argument
184 #define CNST_PMC_VAL(pmc)	(1 << CNST_PMC_SHIFT(pmc))  argument
185 #define CNST_PMC_MASK(pmc)	(2 << CNST_PMC_SHIFT(pmc))  argument
193 #define MMCR1_UNIT_SHIFT(pmc)		(60 - (4 * ((pmc) - 1)))  argument
194 #define MMCR1_COMBINE_SHIFT(pmc)	(35 - ((pmc) - 1))  argument
195 #define MMCR1_PMCSEL_SHIFT(pmc)		(24 - (((pmc) - 1)) * 8)  argument
201 #define p9_MMCR1_COMBINE_SHIFT(pmc)	(38 - ((pmc - 1) * 2))  argument
228 #define MMCR2_FCS(pmc)			(1ull << (63 - (((pmc) - 1) * 9)))  argument
229 #define MMCR2_FCP(pmc)			(1ull << (62 - (((pmc) - 1) * 9)))  argument
230 #define MMCR2_FCH(pmc)			(1ull << (57 - (((pmc) - 1) * 9)))  argument
236 #define MMCR3_SHIFT(pmc)		(49 - (15 * ((pmc) - 1)))  argument
255 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);