40 	struct mmcr_regs mmcr;  member
128 	return cpuhw->mmcr.mmcr0;  in ebb_switch_in()
605 	unsigned long mmcr0 = cpuhw->mmcr.mmcr0;  in ebb_switch_in()
639 	mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2);  in ebb_switch_in()
1255 		val = mmcra = cpuhw->mmcr.mmcra;  in power_pmu_disable()
1260 		if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE)  in power_pmu_disable()
1346 		mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);  in power_pmu_enable()
1347 		mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);  in power_pmu_enable()
1349 			mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);  in power_pmu_enable()
1356 	memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));  in power_pmu_enable()
1359 			       &cpuhw->mmcr, cpuhw->event)) {  in power_pmu_enable()
1373 			cpuhw->mmcr.mmcr0 |= MMCR0_FCP;  in power_pmu_enable()
1375 			cpuhw->mmcr.mmcr0 |= freeze_events_kernel;  in power_pmu_enable()
1377 			cpuhw->mmcr.mmcr0 |= MMCR0_FCHV;  in power_pmu_enable()
1386 	mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);  in power_pmu_enable()
1387 	mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);  in power_pmu_enable()
1388 	mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))  in power_pmu_enable()
1391 		mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2);  in power_pmu_enable()
1394 		mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3);  in power_pmu_enable()
1445 	cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE;  in power_pmu_enable()
1461 	if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) {  in power_pmu_enable()
1463 		mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra);  in power_pmu_enable()
1600 			ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr);  in power_pmu_del()
1621 		cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE);  in power_pmu_del()
2302 	write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0);  in __perf_event_interrupt()
2324 		cpuhw->mmcr.mmcr0 = MMCR0_FC;  in power_pmu_prepare_cpu()