282 static void set_pm_event(u32 ctr, int event, u32 unit_mask)  in set_pm_event()  argument
291 		pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;  in set_pm_event()
292 		p = &(pm_signal[ctr]);  in set_pm_event()
299 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
309 	p = &(pm_signal[ctr]);  in set_pm_event()
315 	pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
316 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);  in set_pm_event()
317 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);  in set_pm_event()
318 	pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);  in set_pm_event()
343 		pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);  in set_pm_event()
345 		pm_regs.pm07_cntrl[ctr] = 0;  in set_pm_event()
424 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)  in enable_ctr()  argument
427 	pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;  in enable_ctr()
428 	cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);  in enable_ctr()
559 static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,  in cell_reg_setup_spu_cycles()  argument
562 	spu_cycle_reset = ctr[0].count;  in cell_reg_setup_spu_cycles()
681 static int cell_reg_setup_spu_events(struct op_counter_config *ctr,  in cell_reg_setup_spu_events()  argument
736 	set_pm_event(0, ctr[0].event, ctr[0].unit_mask);  in cell_reg_setup_spu_events()
738 	reset_value[0] = 0xFFFFFFFF - ctr[0].count;  in cell_reg_setup_spu_events()
750 static int cell_reg_setup_ppu(struct op_counter_config *ctr,  in cell_reg_setup_ppu()  argument
771 		pmc_cntrl[0][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
772 		pmc_cntrl[0][i].masks = ctr[i].unit_mask;  in cell_reg_setup_ppu()
773 		pmc_cntrl[0][i].enabled = ctr[i].enabled;  in cell_reg_setup_ppu()
785 		if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))  in cell_reg_setup_ppu()
786 			pmc_cntrl[1][i].evnts = ctr[i].event + 19;  in cell_reg_setup_ppu()
787 		else if (ctr[i].event == 2203)  in cell_reg_setup_ppu()
788 			pmc_cntrl[1][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
789 		else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))  in cell_reg_setup_ppu()
790 			pmc_cntrl[1][i].evnts = ctr[i].event + 16;  in cell_reg_setup_ppu()
792 			pmc_cntrl[1][i].evnts = ctr[i].event;  in cell_reg_setup_ppu()
794 		pmc_cntrl[1][i].masks = ctr[i].unit_mask;  in cell_reg_setup_ppu()
795 		pmc_cntrl[1][i].enabled = ctr[i].enabled;  in cell_reg_setup_ppu()
813 			reset_value[i] = 0xFFFFFFFF - ctr[i].count;  in cell_reg_setup_ppu()
834 static int cell_reg_setup(struct op_counter_config *ctr,  in cell_reg_setup()  argument
866 	if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {  in cell_reg_setup()
868 		ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);  in cell_reg_setup()
869 	} else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&  in cell_reg_setup()
870 		   (ctr[0].event <= SPU_EVENT_NUM_STOP)) {  in cell_reg_setup()
872 		spu_cycle_reset = ctr[0].count;  in cell_reg_setup()
880 		cell_reg_setup_spu_events(ctr, sys, num_ctrs);  in cell_reg_setup()
883 		ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);  in cell_reg_setup()
1241 static int cell_global_start_spu_cycles(struct op_counter_config *ctr)  in cell_global_start_spu_cycles()  argument
1331 static int cell_global_start_spu_events(struct op_counter_config *ctr)  in cell_global_start_spu_events()  argument
1394 static int cell_global_start_ppu(struct op_counter_config *ctr)  in cell_global_start_ppu()  argument
1440 static int cell_global_start(struct op_counter_config *ctr)  in cell_global_start()  argument
1443 		return cell_global_start_spu_cycles(ctr);  in cell_global_start()
1445 		return cell_global_start_spu_events(ctr);  in cell_global_start()
1447 		return cell_global_start_ppu(ctr);  in cell_global_start()
1479 				      struct op_counter_config *ctr)  in cell_handle_interrupt_spu()  argument
1513 		    && ctr[0].enabled)  in cell_handle_interrupt_spu()
1597 				      struct op_counter_config *ctr)  in cell_handle_interrupt_ppu()  argument
1638 			    && ctr[i].enabled) {  in cell_handle_interrupt_ppu()
1670 				  struct op_counter_config *ctr)  in cell_handle_interrupt()  argument
1673 		cell_handle_interrupt_ppu(regs, ctr);  in cell_handle_interrupt()
1675 		cell_handle_interrupt_spu(regs, ctr);  in cell_handle_interrupt()