34 u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};
50  * Return PA for this VA if it is mapped by a BAT, or 0
55 	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)  in v_block_mapped()
58 	return 0;  in v_block_mapped()
62  * Return VA for a given PA or 0 if not mapped
67 	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)  in p_block_mapped()
72 	return 0;  in p_block_mapped()
80 	for (b = 0; b < n; b++) {  in find_free_bat()
95  *   if base is 0x16000000, max size is 0x02000000).
125 	bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */  in setibat()
126 	bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;  in setibat()
128 		bat[0].batu |= 1;	/* Vp = 1 */  in setibat()
135 	bat[0].batu = 0;  in clearibat()
136 	bat[0].batl = 0;  in clearibat()
208 	for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) {  in mmu_mark_initmem_nx()
235 		mtsrin(mfsrin(i << 28) | 0x10000000, i << 28);  in mmu_mark_initmem_nx()
244 	for (i = 0; i < nb; i++) {  in mmu_mark_rodata_ro()
271 		pr_err("%s: no BAT available for mapping 0x%llx\n", __func__,  in setbat()
278 	    (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))  in setbat()
286 	bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */  in setbat()
295 		bat[0] = bat[1];  in setbat()
297 		bat[0].batu = bat[0].batl = 0;  in setbat()
345 	if (TRAP(current->thread.regs) != 0x300 && TRAP(current->thread.regs) != 0x400)  in update_mmu_cache()
361 	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);  in MMU_init_hw()
385 	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);  in MMU_init_hw()
388 		panic("%s: Failed to allocate %lu bytes align=0x%lx\n",  in MMU_init_hw()
411 		ppc_md.progress("hash:patch", 0x345);  in MMU_init_hw_patch()
413 		ppc_md.progress("hash:done", 0x205);  in MMU_init_hw_patch()
420 	modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);  in MMU_init_hw_patch()
421 	modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6);  in MMU_init_hw_patch()
422 	modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6);  in MMU_init_hw_patch()
423 	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);  in MMU_init_hw_patch()
424 	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);  in MMU_init_hw_patch()
429 	modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);  in MMU_init_hw_patch()
430 	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6);  in MMU_init_hw_patch()
431 	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6);  in MMU_init_hw_patch()
432 	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);  in MMU_init_hw_patch()
438 	/* We don't currently support the first MEMBLOCK not mapping 0  in setup_initial_memory_limit()
441 	BUG_ON(first_memblock_base != 0);  in setup_initial_memory_limit()
448 	pr_info("Hash_size         = 0x%lx\n", Hash_size);  in print_system_hash_info()
450 		pr_info("Hash_mask         = 0x%lx\n", Hash_mask);  in print_system_hash_info()