Lines Matching +full:0 +full:xb
31 #define EFAPU 0x4
33 #define VCT 0x4
34 #define SPFP 0x6
35 #define DPFP 0x7
37 #define EFSADD 0x2c0
38 #define EFSSUB 0x2c1
39 #define EFSABS 0x2c4
40 #define EFSNABS 0x2c5
41 #define EFSNEG 0x2c6
42 #define EFSMUL 0x2c8
43 #define EFSDIV 0x2c9
44 #define EFSCMPGT 0x2cc
45 #define EFSCMPLT 0x2cd
46 #define EFSCMPEQ 0x2ce
47 #define EFSCFD 0x2cf
48 #define EFSCFSI 0x2d1
49 #define EFSCTUI 0x2d4
50 #define EFSCTSI 0x2d5
51 #define EFSCTUF 0x2d6
52 #define EFSCTSF 0x2d7
53 #define EFSCTUIZ 0x2d8
54 #define EFSCTSIZ 0x2da
56 #define EVFSADD 0x280
57 #define EVFSSUB 0x281
58 #define EVFSABS 0x284
59 #define EVFSNABS 0x285
60 #define EVFSNEG 0x286
61 #define EVFSMUL 0x288
62 #define EVFSDIV 0x289
63 #define EVFSCMPGT 0x28c
64 #define EVFSCMPLT 0x28d
65 #define EVFSCMPEQ 0x28e
66 #define EVFSCTUI 0x294
67 #define EVFSCTSI 0x295
68 #define EVFSCTUF 0x296
69 #define EVFSCTSF 0x297
70 #define EVFSCTUIZ 0x298
71 #define EVFSCTSIZ 0x29a
73 #define EFDADD 0x2e0
74 #define EFDSUB 0x2e1
75 #define EFDABS 0x2e4
76 #define EFDNABS 0x2e5
77 #define EFDNEG 0x2e6
78 #define EFDMUL 0x2e8
79 #define EFDDIV 0x2e9
80 #define EFDCTUIDZ 0x2ea
81 #define EFDCTSIDZ 0x2eb
82 #define EFDCMPGT 0x2ec
83 #define EFDCMPLT 0x2ed
84 #define EFDCMPEQ 0x2ee
85 #define EFDCFS 0x2ef
86 #define EFDCTUI 0x2f4
87 #define EFDCTSI 0x2f5
88 #define EFDCTUF 0x2f6
89 #define EFDCTSF 0x2f7
90 #define EFDCTUIZ 0x2f8
91 #define EFDCTSIZ 0x2fa
95 #define XB 4 macro
97 #define NOTYPE 0
115 switch (speinsn & 0x7ff) { in insn_type()
118 case EFSCFD: ret = XB; break; in insn_type()
122 case EFSCTSF: ret = XB; break; in insn_type()
123 case EFSCTSI: ret = XB; break; in insn_type()
124 case EFSCTSIZ: ret = XB; break; in insn_type()
125 case EFSCTUF: ret = XB; break; in insn_type()
126 case EFSCTUI: ret = XB; break; in insn_type()
127 case EFSCTUIZ: ret = XB; break; in insn_type()
133 case EFSCFSI: ret = XB; break; in insn_type()
140 case EVFSCTSF: ret = XB; break; in insn_type()
141 case EVFSCTSI: ret = XB; break; in insn_type()
142 case EVFSCTSIZ: ret = XB; break; in insn_type()
143 case EVFSCTUF: ret = XB; break; in insn_type()
144 case EVFSCTUI: ret = XB; break; in insn_type()
145 case EVFSCTUIZ: ret = XB; break; in insn_type()
154 case EFDCFS: ret = XB; break; in insn_type()
158 case EFDCTSF: ret = XB; break; in insn_type()
159 case EFDCTSI: ret = XB; break; in insn_type()
160 case EFDCTSIDZ: ret = XB; break; in insn_type()
161 case EFDCTSIZ: ret = XB; break; in insn_type()
162 case EFDCTUF: ret = XB; break; in insn_type()
163 case EFDCTUI: ret = XB; break; in insn_type()
164 case EFDCTUIDZ: ret = XB; break; in insn_type()
165 case EFDCTUIZ: ret = XB; break; in insn_type()
193 func = speinsn & 0x7ff; in do_spe_mathemu()
194 fc = (speinsn >> 21) & 0x1f; in do_spe_mathemu()
195 fa = (speinsn >> 16) & 0x1f; in do_spe_mathemu()
196 fb = (speinsn >> 11) & 0x1f; in do_spe_mathemu()
197 src = (speinsn >> 5) & 0x7; in do_spe_mathemu()
199 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
209 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
210 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
211 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
221 case XB: in do_spe_mathemu()
262 cmp = 0; in do_spe_mathemu()
276 vc.wp[1] = 0; in do_spe_mathemu()
300 vc.wp[1] = 0; in do_spe_mathemu()
304 ((func & 0x3) != 0)); in do_spe_mathemu()
311 vc.wp[1] = 0; in do_spe_mathemu()
315 ((func & 0x3) != 0)); in do_spe_mathemu()
335 IR = 0x4; in do_spe_mathemu()
337 IR = 0; in do_spe_mathemu()
349 case XB: in do_spe_mathemu()
364 vc.dp[0] = va.dp[0] & ~SIGN_BIT_D; in do_spe_mathemu()
368 vc.dp[0] = va.dp[0] | SIGN_BIT_D; in do_spe_mathemu()
372 vc.dp[0] = va.dp[0] ^ SIGN_BIT_D; in do_spe_mathemu()
392 cmp = 0; in do_spe_mathemu()
406 vc.wp[1] = 0; in do_spe_mathemu()
430 vc.dp[0] = 0; in do_spe_mathemu()
433 FP_TO_INT_D(vc.dp[0], DB, 64, in do_spe_mathemu()
434 ((func & 0x1) == 0)); in do_spe_mathemu()
441 vc.wp[1] = 0; in do_spe_mathemu()
445 ((func & 0x3) != 0)); in do_spe_mathemu()
452 vc.wp[1] = 0; in do_spe_mathemu()
456 ((func & 0x3) != 0)); in do_spe_mathemu()
477 IR = 0x4; in do_spe_mathemu()
479 IR = 0; in do_spe_mathemu()
495 case XB: in do_spe_mathemu()
516 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; in do_spe_mathemu()
521 vc.wp[0] = va.wp[0] | SIGN_BIT_S; in do_spe_mathemu()
526 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; in do_spe_mathemu()
551 cmp = 0; in do_spe_mathemu()
565 vc.wp[0] = 0; in do_spe_mathemu()
569 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
573 vc.wp[1] = 0; in do_spe_mathemu()
585 vc.wp[0] = 0; in do_spe_mathemu()
588 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
589 ((func & 0x3) != 0)); in do_spe_mathemu()
592 vc.wp[1] = 0; in do_spe_mathemu()
596 ((func & 0x3) != 0)); in do_spe_mathemu()
603 vc.wp[0] = 0; in do_spe_mathemu()
606 FP_TO_INT_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
607 ((func & 0x3) != 0)); in do_spe_mathemu()
610 vc.wp[1] = 0; in do_spe_mathemu()
614 ((func & 0x3) != 0)); in do_spe_mathemu()
643 ch = (IR0 == cmp) ? 1 : 0; in do_spe_mathemu()
644 cl = (IR1 == cmp) ? 1 : 0; in do_spe_mathemu()
646 ((ch & cl) << 0); in do_spe_mathemu()
655 regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2)); in do_spe_mathemu()
656 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2)); in do_spe_mathemu()
681 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
687 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
688 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
689 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
708 return 0; in do_spe_mathemu()
715 return 0; in do_spe_mathemu()
735 func = speinsn & 0x7ff; in speround_handler()
742 fptype = (speinsn >> 5) & 0x7; in speround_handler()
748 return 0; in speround_handler()
750 fc = (speinsn >> 21) & 0x1f; in speround_handler()
753 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
756 fb = (speinsn >> 11) & 0x1f; in speround_handler()
770 return 0; in speround_handler()
778 fp_result = 0; in speround_handler()
779 s_lo = 0; in speround_handler()
780 s_hi = 0; in speround_handler()
785 fp_result = 0; in speround_handler()
787 if (fgpr.wp[1] == 0) in speround_handler()
793 fp_result = 0; in speround_handler()
795 if (fgpr.wp[1] == 0) in speround_handler()
797 if (fgpr.wp[0] == 0) in speround_handler()
803 fp_result = 0; in speround_handler()
806 if (fgpr.wp[1] == 0) in speround_handler()
815 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
824 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
828 fgpr.wp[1]++; /* Z < 0, choose Z2 */ in speround_handler()
830 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
839 fgpr.dp[0]++; /* Z > 0, choose Z1 */ in speround_handler()
841 fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
846 fgpr.dp[0]++; /* Z < 0, choose Z2 */ in speround_handler()
848 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
856 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ in speround_handler()
858 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ in speround_handler()
862 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ in speround_handler()
864 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ in speround_handler()
868 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ in speround_handler()
870 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ in speround_handler()
879 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
882 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
885 return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0; in speround_handler()
886 return 0; in speround_handler()
924 return 0; in spe_mathemu_init()