Lines Matching +full:0 +full:x5400
25 #define EX_R9 0
109 * Branch to label using its 0xC000 address. This results in instruction
110 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
113 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
158 IHSRR=0
161 IHSRR_IF_HVMODE=0
170 IISIDE=0
173 IDAR=0
176 IDSISR=0
185 IREALMODE_COMMON=0
188 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
192 IMASK=0
195 IKVM_SKIP=0
198 IKVM_REAL=0
201 IKVM_VIRT=0
222 * taken with MSR[HV]=0.
231 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
232 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
236 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
255 cmpwi r10,0
285 /* HSRR variants have the 0x2 bit added to their trap number */
288 ori r12,r12,(IVEC + 0x2)
293 ori r12,r12,(IVEC+ 0x2)
300 89: mtocrf 0x80,r9
371 .macro GEN_INT_ENTRY name, virt, ool=0
530 .if IVEC == 0x500 || IVEC == 0xea0
532 .elseif IVEC == 0x900
534 .elseif IVEC == 0xa00 || IVEC == 0xe80
536 .elseif IVEC == 0xe60
538 .elseif IVEC == 0xf00
564 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
570 std r10,0(r1) /* make stack chain pointer */
648 li r10,0
667 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
679 .macro EXCEPTION_RESTORE_REGS hsrr=0
703 REST_GPR(0, r1)
738 * - Virtual mode exceptions must be mapped at their 0xc000... location.
742 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
743 * virtual 0xc00...
753 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
759 * The scv instructions are a special case. They get a 0x3000 offset applied.
762 * It's impossible to receive interrupts below 0x300 via AIL.
765 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
769 * 0x0000 - 0x00ff : Secondary processor spin code
770 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
771 * 0x1900 - 0x2fff : Real mode trampolines
772 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
773 * 0x5900 - 0x6fff : Relon mode trampolines
774 * 0x7000 - 0x7fff : FWNMI data area
775 * 0x8000 - .... : Common interrupt handlers, remaining early
778 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
782 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
783 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
784 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
785 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
797 * This address (0x7000) is fixed by the RPA.
799 * 0x7000 to 0x8000 free for use by the firmware
801 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
802 OPEN_TEXT_SECTION(0x8000)
804 OPEN_TEXT_SECTION(0x7000)
813 * address 0x100 when we are running a relocatable kernel.
821 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
832 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
833 * ensure scv is never executed with relocation off, which means AIL-0
846 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
847 /* SCV 0 */
876 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
891 /* No virt vectors corresponding with 0x0..0x100 */
892 EXC_VIRT_NONE(0x4000, 0x100)
896 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
921 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
929 IVEC=0x100
931 IVIRT=0 /* no virt entry point */
936 ISET_RI=0
937 ISTACK=0
938 IRECONCILE=0
942 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
947 * bits 46:47. A non-0 value indicates that we are coming from a power
949 * but we branch to the 0xc000... address so we can turn on relocation
963 std r3,PACA_EXNMI+0*8(r13)
967 mfocrf r4,0x80
971 mtocrf 0x80,r4
972 ld r3,PACA_EXNMI+0*8(r13)
979 GEN_INT_ENTRY system_reset, virt=0
987 EXC_REAL_END(system_reset, 0x100, 0x100)
988 EXC_VIRT_NONE(0x4100, 0x100)
1003 GEN_INT_ENTRY system_reset, virt=0
1031 * as we are running with MSR[EE]=0.
1044 li r9,0
1070 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1113 IVEC=0x200
1115 IVIRT=0 /* no virt entry point */
1122 ISET_RI=0
1123 ISTACK=0
1126 IRECONCILE=0
1127 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1131 IVEC=0x200
1133 IVIRT=0 /* no virt entry point */
1134 ISET_RI=0
1141 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1142 GEN_INT_ENTRY machine_check_early, virt=0
1143 EXC_REAL_END(machine_check, 0x200, 0x100)
1144 EXC_VIRT_NONE(0x4200, 0x100)
1149 GEN_INT_ENTRY machine_check_early, virt=0
1154 li r9,0; \
1178 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1187 cmpwi r10,0 /* Are we in nested machine check */
1256 cmpwi r11,0 /* Check if coming from guest */
1281 cmpdi r3,0 /* see if we handled MCE successfully */
1306 GEN_INT_ENTRY machine_check, virt=0
1369 li r10,0 /* clear MSR_RI */
1396 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1425 IVEC=0x300
1432 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1433 GEN_INT_ENTRY data_access, virt=0
1434 EXC_REAL_END(data_access, 0x300, 0x80)
1435 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1437 EXC_VIRT_END(data_access, 0x4300, 0x80)
1444 li r3,0x300
1454 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1468 * KVM: Same as 0x300, DSLB must test for KVM guest.
1474 IVEC=0x380
1476 IRECONCILE=0
1482 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1483 GEN_INT_ENTRY data_access_slb, virt=0
1484 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1485 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1487 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1495 cmpdi r3,0
1515 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1524 IVEC=0x400
1533 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1534 GEN_INT_ENTRY instruction_access, virt=0
1535 EXC_REAL_END(instruction_access, 0x400, 0x80)
1536 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1538 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1545 li r3,0x400
1555 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1564 IVEC=0x480
1566 IRECONCILE=0
1574 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1575 GEN_INT_ENTRY instruction_access_slb, virt=0
1576 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1577 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1579 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1587 cmpdi r3,0
1607 * Interrupt 0x500 - External Interrupt.
1630 IVEC=0x500
1637 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1638 GEN_INT_ENTRY hardware_interrupt, virt=0
1639 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1640 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1642 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1655 * Interrupt 0x600 - Alignment Interrupt
1659 IVEC=0x600
1667 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1668 GEN_INT_ENTRY alignment, virt=0
1669 EXC_REAL_END(alignment, 0x600, 0x100)
1670 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1672 EXC_VIRT_END(alignment, 0x4600, 0x100)
1684 * Interrupt 0x700 - Program Interrupt (program check).
1693 IVEC=0x700
1699 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1700 GEN_INT_ENTRY program_check, virt=0
1701 EXC_REAL_END(program_check, 0x700, 0x100)
1702 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1704 EXC_VIRT_END(program_check, 0x4700, 0x100)
1732 __ISTACK(program_check)=0
1748 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1750 * with MSR[FP]=0.
1757 IVEC=0x800
1758 IRECONCILE=0
1764 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1765 GEN_INT_ENTRY fp_unavailable, virt=0
1766 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1767 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1769 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1776 0: trap
1777 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1802 * Interrupt 0x900 - Decrementer Interrupt.
1809 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1819 IVEC=0x900
1826 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1827 GEN_INT_ENTRY decrementer, virt=0
1828 EXC_REAL_END(decrementer, 0x900, 0x80)
1829 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1831 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1844 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1845 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1854 IVEC=0x980
1856 ISTACK=0
1857 IRECONCILE=0
1862 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1863 GEN_INT_ENTRY hdecrementer, virt=0
1864 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1865 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1867 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1880 mtcrf 0x80,r9
1892 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1899 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1906 IVEC=0xa00
1913 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1914 GEN_INT_ENTRY doorbell_super, virt=0
1915 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1916 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1918 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1934 EXC_REAL_NONE(0xb00, 0x100)
1935 EXC_VIRT_NONE(0x4b00, 0x100)
1938 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1940 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1944 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1945 * 0x4c00 virtual mode.
1963 IVEC=0xc00
1992 cmpdi r0,0x1ebe
2012 mtmsrd r10,1 /* Set RI (EE=0) */
2033 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2034 SYSTEM_CALL 0
2035 EXC_REAL_END(system_call, 0xc00, 0x100)
2036 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2038 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2064 ori r12,r12,0xc00
2082 * Interrupt 0xd00 - Trace Interrupt.
2087 IVEC=0xd00
2093 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2094 GEN_INT_ENTRY single_step, virt=0
2095 EXC_REAL_END(single_step, 0xd00, 0x100)
2096 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2098 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2109 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2121 IVEC=0xe00
2130 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2131 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2132 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2133 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2135 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2152 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2157 IVEC=0xe20
2163 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2164 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2165 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2166 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2168 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2179 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2182 IVEC=0xe40
2188 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2189 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2190 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2191 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2193 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2205 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2229 IVEC=0xe60
2232 ISTACK=0
2233 IRECONCILE=0
2234 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2239 IVEC=0xe60
2245 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2246 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2247 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2248 EXC_VIRT_NONE(0x4e60, 0x20)
2261 cmpdi cr0,r3,0
2273 GEN_INT_ENTRY hmi_exception, virt=0
2289 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2291 * Similar to the 0xa00 doorbell but for host rather than guest.
2294 IVEC=0xe80
2301 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2302 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2303 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2304 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2306 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2323 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2325 * Similar to 0x500 but for host only.
2328 IVEC=0xea0
2335 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2336 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2337 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2338 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2340 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2352 EXC_REAL_NONE(0xec0, 0x20)
2353 EXC_VIRT_NONE(0x4ec0, 0x20)
2354 EXC_REAL_NONE(0xee0, 0x20)
2355 EXC_VIRT_NONE(0x4ee0, 0x20)
2359 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2375 IVEC=0xf00
2382 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2383 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2384 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2385 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2387 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2400 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2402 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2406 IVEC=0xf20
2407 IRECONCILE=0
2413 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2414 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2415 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2416 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2418 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2454 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2456 * executing a VSX instruction with MSR[VSX]=0.
2460 IVEC=0xf40
2461 IRECONCILE=0
2467 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2468 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2469 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2470 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2472 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2507 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2514 IVEC=0xf60
2520 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2521 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2522 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2523 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2525 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2537 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2544 IVEC=0xf80
2550 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2551 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2552 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2553 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2555 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2566 EXC_REAL_NONE(0xfa0, 0x20)
2567 EXC_VIRT_NONE(0x4fa0, 0x20)
2568 EXC_REAL_NONE(0xfc0, 0x20)
2569 EXC_VIRT_NONE(0x4fc0, 0x20)
2570 EXC_REAL_NONE(0xfe0, 0x20)
2571 EXC_VIRT_NONE(0x4fe0, 0x20)
2573 EXC_REAL_NONE(0x1000, 0x100)
2574 EXC_VIRT_NONE(0x5000, 0x100)
2575 EXC_REAL_NONE(0x1100, 0x100)
2576 EXC_VIRT_NONE(0x5100, 0x100)
2580 IVEC=0x1200
2586 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2587 GEN_INT_ENTRY cbe_system_error, virt=0
2588 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2589 EXC_VIRT_NONE(0x5200, 0x100)
2599 EXC_REAL_NONE(0x1200, 0x100)
2600 EXC_VIRT_NONE(0x5200, 0x100)
2605 IVEC=0x1300
2612 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2613 GEN_INT_ENTRY instruction_breakpoint, virt=0
2614 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2615 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2617 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2627 EXC_REAL_NONE(0x1400, 0x100)
2628 EXC_VIRT_NONE(0x5400, 0x100)
2631 * Interrupt 0x1500 - Soft Patch Interrupt
2643 IVEC=0x1500
2645 IBRANCH_TO_COMMON=0
2649 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2650 GEN_INT_ENTRY denorm_exception, virt=0
2655 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2656 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2658 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2663 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2665 EXC_VIRT_NONE(0x5500, 0x100)
2681 .Lreg=0
2697 .Lreg=0
2722 mtcrf 0x80,r9
2751 IVEC=0x1600
2757 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2758 GEN_INT_ENTRY cbe_maintenance, virt=0
2759 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2760 EXC_VIRT_NONE(0x5600, 0x100)
2770 EXC_REAL_NONE(0x1600, 0x100)
2771 EXC_VIRT_NONE(0x5600, 0x100)
2776 IVEC=0x1700
2782 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2783 GEN_INT_ENTRY altivec_assist, virt=0
2784 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2785 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2787 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2804 IVEC=0x1800
2810 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2811 GEN_INT_ENTRY cbe_thermal, virt=0
2812 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2813 EXC_VIRT_NONE(0x5800, 0x100)
2823 EXC_REAL_NONE(0x1800, 0x100)
2824 EXC_VIRT_NONE(0x5800, 0x100)
2831 IVEC=0x900
2832 ISTACK=0
2833 IRECONCILE=0 /* Soft-NMI may fire under local_irq_disable */
2867 li r9,0
2879 EXCEPTION_RESTORE_REGS hsrr=0
2894 .macro MASKED_INTERRUPT hsrr=0
2905 lis r10,0x7fff
2906 ori r10,r10,0xffff
2926 mtcrf 0x80,r9
2948 ori 31,31,0
2972 ld r11,(0x80 + 8)*0(r10)
2973 ld r11,(0x80 + 8)*1(r10)
2974 ld r11,(0x80 + 8)*2(r10)
2975 ld r11,(0x80 + 8)*3(r10)
2976 ld r11,(0x80 + 8)*4(r10)
2977 ld r11,(0x80 + 8)*5(r10)
2978 ld r11,(0x80 + 8)*6(r10)
2979 ld r11,(0x80 + 8)*7(r10)
2980 addi r10,r10,0x80*8
3054 ld r11,(0x80 + 8)*0(r10)
3055 ld r11,(0x80 + 8)*1(r10)
3056 ld r11,(0x80 + 8)*2(r10)
3057 ld r11,(0x80 + 8)*3(r10)
3058 ld r11,(0x80 + 8)*4(r10)
3059 ld r11,(0x80 + 8)*5(r10)
3060 ld r11,(0x80 + 8)*6(r10)
3061 ld r11,(0x80 + 8)*7(r10)
3062 addi r10,r10,0x80*8
3066 li r9,0
3067 li r10,0
3068 li r11,0
3120 * offset by 0xc000000000004000.
3121 * It's impossible to receive interrupts below 0x300 via this mechanism.
3123 * to HV=1 from HV=0 is delivered via real mode handlers.
3127 * This uses the standard macro, since the original 0x300 vector
3142 * handlers, so that they are copied to real address 0x100 when running
3144 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3181 0: mflr r3
3182 addi r3,r3,(1f - 0b)
3195 0: mflr r3
3196 addi r3,r3,(1f - 0b)
3235 * at return r3 = 0 for success, 1 for page fault, negative for error
3238 cmpdi r3,0 /* see if __hash_page succeeded */
3257 cmpdi r3,0