Lines Matching +full:used +full:- +full:by +full:- +full:rtas
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
25 #include <asm/code-patching-asm.h>
27 #include <asm/asm-offsets.h>
36 #include <asm/ppc-opcode.h>
39 #include <asm/asm-compat.h>
41 #include <asm/exception-64s.h>
43 #include <asm/exception-64e.h>
45 #include <asm/feature-fixups.h>
60 /* This value is used to mark exception frames on the stack. */
74 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
90 /* Can we avoid saving r3-r8 in common case? */
97 /* Zero r9-r12, this should only be required when restoring all GPRs */
114 std r11,-16(r10) /* "regshere" marker */
154 /* rfscv returns with LR->NIA and CTR->MSR */
211 * which is tested by system_call_exception when r0 is -1 (as set by vector
218 * Entered via kernel return set up by kernel/sstep.c, must match entry regs
234 extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
254 /* Can we avoid saving r3-r8 in common case? */
261 /* Zero r9-r12, this should only be required when restoring all GPRs */
276 rldimi r12,r11,28,(63-28)
284 std r11,-16(r10) /* "regshere" marker */
368 rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
417 /* Save non-volatile GPRs, if not already saved. */
421 beqlr-
497 * of this code; either by coming in via the entry (_switch)
509 stdu r1,-SWITCH_FRAME_SIZE(r1)
510 /* r3-r13 are caller saved -- Cort */
527 * scheduled on CPUy by virtue of the core scheduler barriers
528 * (see "Notes on Program-Order guarantees on SMP systems." in
552 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
579 ori r0,r0,(SLB_NUM_BOLTED-1)@l
616 because we don't need to leave the 288-byte ABI gap at the
618 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
634 /* r3-r13 are destroyed -- Cort */
638 addi r3,r3,-THREAD
647 * touched, no exit work created, then this can be used.
675 bne- .Lrestore_nvgprs
754 std r0,STACK_FRAME_OVERHEAD-16(r1)
758 bne- cr1,1f /* emulate stack store */
768 * and updated in our interrupt regs by emulate_loadstore, but we can't
769 * store the previous value of r1 to the stack before re-loading our
789 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
794 * Note: r3 is an input parameter to rtas, so don't trash it...
799 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
801 /* Because RTAS is running in 32b mode, it clobbers the high order half
803 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
807 SAVE_NVGPRS(r1) /* Save the non-volatiles */
820 /* Temporary workaround to clear CR until RTAS can be modified to
835 /* Hard-disable interrupts */
843 * our original state after RTAS returns.
858 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
866 LOAD_REG_ADDR(r4, rtas)
867 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
868 ld r4,RTASBASE(r4) /* get the rtas->base value */
884 sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
895 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
914 REST_NVGPRS(r1) /* Restore the non-volatiles */
940 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
944 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
960 addi r4,r4,(1f - 0b)
963 /* Prepare a 32-bit mode big endian MSR
980 * corrupt by OF