176 			edev->pe->phb->global_number, edev->bdfn >> 8,  in eeh_dump_dev_log()
179 		edev->pe->phb->global_number, edev->bdfn >> 8,  in eeh_dump_dev_log()
269 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)  in eeh_dump_pe_log()  argument
274 	eeh_pe_for_each_dev(pe, edev, tmp)  in eeh_dump_pe_log()
291 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)  in eeh_slot_error_detail()  argument
311 	if (!(pe->type & EEH_PE_PHB)) {  in eeh_slot_error_detail()
314 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);  in eeh_slot_error_detail()
328 		eeh_ops->configure_bridge(pe);  in eeh_slot_error_detail()
329 		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {  in eeh_slot_error_detail()
330 			eeh_pe_restore_bars(pe);  in eeh_slot_error_detail()
333 			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);  in eeh_slot_error_detail()
337 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);  in eeh_slot_error_detail()
381 static int eeh_phb_check_failure(struct eeh_pe *pe)  in eeh_phb_check_failure()  argument
391 	phb_pe = eeh_phb_pe_get(pe->phb);  in eeh_phb_check_failure()
394 			__func__, pe->phb->global_number);  in eeh_phb_check_failure()
446 	struct eeh_pe *pe, *parent_pe;  in eeh_dev_check_failure()  local
460 	pe = eeh_dev_to_pe(edev);  in eeh_dev_check_failure()
463 	if (!pe) {  in eeh_dev_check_failure()
473 	ret = eeh_phb_check_failure(pe);  in eeh_dev_check_failure()
482 	if (eeh_pe_passed(pe))  in eeh_dev_check_failure()
493 	if (pe->state & EEH_PE_ISOLATED) {  in eeh_dev_check_failure()
494 		pe->check_count++;  in eeh_dev_check_failure()
495 		if (pe->check_count == EEH_MAX_FAILS) {  in eeh_dev_check_failure()
501 				pe->check_count,  in eeh_dev_check_failure()
518 	ret = eeh_ops->get_state(pe, NULL);  in eeh_dev_check_failure()
529 		pe->false_positives++;  in eeh_dev_check_failure()
539 	parent_pe = pe->parent;  in eeh_dev_check_failure()
548 			pe = parent_pe;  in eeh_dev_check_failure()
550 			       pe->phb->global_number, pe->addr,  in eeh_dev_check_failure()
551 			       pe->phb->global_number, parent_pe->addr);  in eeh_dev_check_failure()
564 	eeh_pe_mark_isolated(pe);  in eeh_dev_check_failure()
572 		__func__, pe->phb->global_number, pe->addr);  in eeh_dev_check_failure()
573 	eeh_send_failure_event(pe);  in eeh_dev_check_failure()
621 int eeh_pci_enable(struct eeh_pe *pe, int function)  in eeh_pci_enable()  argument
653 		rc = eeh_ops->get_state(pe, NULL);  in eeh_pci_enable()
668 	rc = eeh_ops->set_option(pe, function);  in eeh_pci_enable()
672 			__func__, function, pe->phb->global_number,  in eeh_pci_enable()
673 			pe->addr, rc);  in eeh_pci_enable()
677 		rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_pci_enable()
744 	struct eeh_pe *pe = eeh_dev_to_pe(edev);  in pcibios_set_pcie_reset_state()  local
746 	if (!pe) {  in pcibios_set_pcie_reset_state()
754 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);  in pcibios_set_pcie_reset_state()
755 		eeh_unfreeze_pe(pe);  in pcibios_set_pcie_reset_state()
756 		if (!(pe->type & EEH_PE_VF))  in pcibios_set_pcie_reset_state()
757 			eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);  in pcibios_set_pcie_reset_state()
758 		eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);  in pcibios_set_pcie_reset_state()
759 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);  in pcibios_set_pcie_reset_state()
762 		eeh_pe_mark_isolated(pe);  in pcibios_set_pcie_reset_state()
763 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);  in pcibios_set_pcie_reset_state()
764 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
765 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);  in pcibios_set_pcie_reset_state()
766 		if (!(pe->type & EEH_PE_VF))  in pcibios_set_pcie_reset_state()
767 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
768 		eeh_ops->reset(pe, EEH_RESET_HOT);  in pcibios_set_pcie_reset_state()
771 		eeh_pe_mark_isolated(pe);  in pcibios_set_pcie_reset_state()
772 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);  in pcibios_set_pcie_reset_state()
773 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in pcibios_set_pcie_reset_state()
774 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);  in pcibios_set_pcie_reset_state()
775 		if (!(pe->type & EEH_PE_VF))  in pcibios_set_pcie_reset_state()
776 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in pcibios_set_pcie_reset_state()
777 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);  in pcibios_set_pcie_reset_state()
780 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);  in pcibios_set_pcie_reset_state()
809 	struct eeh_pe *pe;  in eeh_pe_refreeze_passed()  local
812 	eeh_for_each_pe(root, pe) {  in eeh_pe_refreeze_passed()
813 		if (eeh_pe_passed(pe)) {  in eeh_pe_refreeze_passed()
814 			state = eeh_ops->get_state(pe, NULL);  in eeh_pe_refreeze_passed()
818 					pe->phb->global_number, pe->addr);  in eeh_pe_refreeze_passed()
819 				eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);  in eeh_pe_refreeze_passed()
837 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)  in eeh_pe_reset_full()  argument
849 	eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);  in eeh_pe_reset_full()
855 	eeh_pe_state_mark(pe, reset_state);  in eeh_pe_reset_full()
859 		ret = eeh_pe_reset(pe, type, include_passed);  in eeh_pe_reset_full()
861 			ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,  in eeh_pe_reset_full()
866 				state, pe->phb->global_number, pe->addr, i + 1);  in eeh_pe_reset_full()
871 				pe->phb->global_number, pe->addr, i + 1);  in eeh_pe_reset_full()
874 		state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);  in eeh_pe_reset_full()
877 				pe->phb->global_number, pe->addr);  in eeh_pe_reset_full()
885 				pe->phb->global_number, pe->addr, state, i + 1);  in eeh_pe_reset_full()
892 		eeh_pe_refreeze_passed(pe);  in eeh_pe_reset_full()
894 	eeh_pe_state_clear(pe, reset_state, true);  in eeh_pe_reset_full()
1082 	if (!edev || !edev->pdev || !edev->pe) {  in eeh_remove_device()
1120 	if (!(edev->pe->state & EEH_PE_KEEP))  in eeh_remove_device()
1126 int eeh_unfreeze_pe(struct eeh_pe *pe)  in eeh_unfreeze_pe()  argument
1130 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);  in eeh_unfreeze_pe()
1133 			__func__, ret, pe->phb->global_number, pe->addr);  in eeh_unfreeze_pe()
1137 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);  in eeh_unfreeze_pe()
1140 			__func__, ret, pe->phb->global_number, pe->addr);  in eeh_unfreeze_pe()
1155 static int eeh_pe_change_owner(struct eeh_pe *pe)  in eeh_pe_change_owner()  argument
1163 	ret = eeh_ops->get_state(pe, NULL);  in eeh_pe_change_owner()
1172 	eeh_pe_for_each_dev(pe, edev, tmp) {  in eeh_pe_change_owner()
1191 			return eeh_pe_reset_and_recover(pe);  in eeh_pe_change_owner()
1195 	ret = eeh_unfreeze_pe(pe);  in eeh_pe_change_owner()
1197 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);  in eeh_pe_change_owner()
1223 	if (!edev || !edev->pe)  in eeh_dev_open()
1232 	ret = eeh_pe_change_owner(edev->pe);  in eeh_dev_open()
1237 	atomic_inc(&edev->pe->pass_dev_cnt);  in eeh_dev_open()
1267 	if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))  in eeh_dev_release()
1271 	WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);  in eeh_dev_release()
1272 	eeh_pe_change_owner(edev->pe);  in eeh_dev_release()
1318 	if (!edev || !edev->pe)  in eeh_iommu_group_to_pe()
1321 	return edev->pe;  in eeh_iommu_group_to_pe()
1335 int eeh_pe_set_option(struct eeh_pe *pe, int option)  in eeh_pe_set_option()  argument
1340 	if (!pe)  in eeh_pe_set_option()
1351 			ret = eeh_pe_change_owner(pe);  in eeh_pe_set_option()
1366 		ret = eeh_pci_enable(pe, option);  in eeh_pe_set_option()
1385 int eeh_pe_get_state(struct eeh_pe *pe)  in eeh_pe_get_state()  argument
1391 	if (!pe)  in eeh_pe_get_state()
1403 	if (pe->parent &&  in eeh_pe_get_state()
1404 	    !(pe->state & EEH_PE_REMOVED) &&  in eeh_pe_get_state()
1405 	    (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))  in eeh_pe_get_state()
1408 	result = eeh_ops->get_state(pe, NULL);  in eeh_pe_get_state()
1428 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)  in eeh_pe_reenable_devices()  argument
1434 	eeh_pe_restore_bars(pe);  in eeh_pe_reenable_devices()
1440 	eeh_pe_for_each_dev(pe, edev, tmp) {  in eeh_pe_reenable_devices()
1454 	if (include_passed || !eeh_pe_passed(pe)) {  in eeh_pe_reenable_devices()
1455 		ret = eeh_unfreeze_pe(pe);  in eeh_pe_reenable_devices()
1458 			pe->phb->global_number, pe->addr);  in eeh_pe_reenable_devices()
1460 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);  in eeh_pe_reenable_devices()
1474 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)  in eeh_pe_reset()  argument
1479 	if (!pe)  in eeh_pe_reset()
1487 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1488 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);  in eeh_pe_reset()
1492 		ret = eeh_pe_reenable_devices(pe, include_passed);  in eeh_pe_reset()
1501 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);  in eeh_pe_reset()
1503 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);  in eeh_pe_reset()
1504 		ret = eeh_ops->reset(pe, option);  in eeh_pe_reset()
1524 int eeh_pe_configure(struct eeh_pe *pe)  in eeh_pe_configure()  argument
1529 	if (!pe)  in eeh_pe_configure()
1548 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,  in eeh_pe_inject_err()  argument
1552 	if (!pe)  in eeh_pe_inject_err()
1567 	return eeh_ops->err_inject(pe, type, func, addr, mask);  in eeh_pe_inject_err()
1627 	struct eeh_pe *pe;  in eeh_force_recover_write()  local
1655 	pe = eeh_pe_get(hose, pe_no);  in eeh_force_recover_write()
1656 	if (!pe)  in eeh_force_recover_write()
1666 	__eeh_send_failure_event(pe);  in eeh_force_recover_write()