Lines Matching +full:0 +full:x00000
14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
29 * 0b10 = reserved
30 * 0b11 = External proxy / coreint
32 #define MPIC_GREG_GCONF_COREINT 0x60000000
33 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
34 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000
35 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
36 #define MPIC_GREG_GCONF_MCK 0x08000000
37 #define MPIC_GREG_GLOBAL_CONF_1 0x00030
38 #define MPIC_GREG_VENDOR_0 0x00040
39 #define MPIC_GREG_VENDOR_1 0x00050
40 #define MPIC_GREG_VENDOR_2 0x00060
41 #define MPIC_GREG_VENDOR_3 0x00070
42 #define MPIC_GREG_VENDOR_ID 0x00080
43 #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
45 #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
47 #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
48 #define MPIC_GREG_PROCESSOR_INIT 0x00090
49 #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
50 #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
51 #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
52 #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
53 #define MPIC_GREG_IPI_STRIDE 0x10
54 #define MPIC_GREG_SPURIOUS 0x000e0
55 #define MPIC_GREG_TIMER_FREQ 0x000f0
61 #define MPIC_TIMER_BASE 0x01100
62 #define MPIC_TIMER_STRIDE 0x40
63 #define MPIC_TIMER_GROUP_STRIDE 0x1000
65 #define MPIC_TIMER_CURRENT_CNT 0x00000
66 #define MPIC_TIMER_BASE_CNT 0x00010
67 #define MPIC_TIMER_VECTOR_PRI 0x00020
68 #define MPIC_TIMER_DESTINATION 0x00030
74 #define MPIC_CPU_THISBASE 0x00000
75 #define MPIC_CPU_BASE 0x20000
76 #define MPIC_CPU_STRIDE 0x01000
78 #define MPIC_CPU_IPI_DISPATCH_0 0x00040
79 #define MPIC_CPU_IPI_DISPATCH_1 0x00050
80 #define MPIC_CPU_IPI_DISPATCH_2 0x00060
81 #define MPIC_CPU_IPI_DISPATCH_3 0x00070
82 #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
83 #define MPIC_CPU_CURRENT_TASK_PRI 0x00080
84 #define MPIC_CPU_TASKPRI_MASK 0x0000000f
85 #define MPIC_CPU_WHOAMI 0x00090
86 #define MPIC_CPU_WHOAMI_MASK 0x0000001f
87 #define MPIC_CPU_INTACK 0x000a0
88 #define MPIC_CPU_EOI 0x000b0
89 #define MPIC_CPU_MCACK 0x000c0
95 #define MPIC_IRQ_BASE 0x10000
96 #define MPIC_IRQ_STRIDE 0x00020
97 #define MPIC_IRQ_VECTOR_PRI 0x00000
98 #define MPIC_VECPRI_MASK 0x80000000
99 #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
100 #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
102 #define MPIC_VECPRI_VECTOR_MASK 0x000007ff
103 #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
104 #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
105 #define MPIC_VECPRI_POLARITY_MASK 0x00800000
106 #define MPIC_VECPRI_SENSE_LEVEL 0x00400000
107 #define MPIC_VECPRI_SENSE_EDGE 0x00000000
108 #define MPIC_VECPRI_SENSE_MASK 0x00400000
109 #define MPIC_IRQ_DESTINATION 0x00010
111 #define MPIC_FSL_BRR1 0x00000
112 #define MPIC_FSL_BRR1_VER 0x0000ffff
129 #define TSI108_GREG_BASE 0x00000
130 #define TSI108_GREG_FEATURE_0 0x00000
131 #define TSI108_GREG_GLOBAL_CONF_0 0x00004
132 #define TSI108_GREG_VENDOR_ID 0x0000c
133 #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
134 #define TSI108_GREG_IPI_STRIDE 0x0c
135 #define TSI108_GREG_SPURIOUS 0x00010
136 #define TSI108_GREG_TIMER_FREQ 0x00014
141 #define TSI108_TIMER_BASE 0x0030
142 #define TSI108_TIMER_STRIDE 0x10
143 #define TSI108_TIMER_CURRENT_CNT 0x00000
144 #define TSI108_TIMER_BASE_CNT 0x00004
145 #define TSI108_TIMER_VECTOR_PRI 0x00008
146 #define TSI108_TIMER_DESTINATION 0x0000c
151 #define TSI108_CPU_BASE 0x00300
152 #define TSI108_CPU_STRIDE 0x00040
153 #define TSI108_CPU_IPI_DISPATCH_0 0x00200
154 #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
155 #define TSI108_CPU_CURRENT_TASK_PRI 0x00000
156 #define TSI108_CPU_WHOAMI 0xffffffff
157 #define TSI108_CPU_INTACK 0x00004
158 #define TSI108_CPU_EOI 0x00008
159 #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
164 #define TSI108_IRQ_BASE 0x00100
165 #define TSI108_IRQ_STRIDE 0x00008
166 #define TSI108_IRQ_VECTOR_PRI 0x00000
167 #define TSI108_VECPRI_VECTOR_MASK 0x000000ff
168 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
169 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
170 #define TSI108_VECPRI_SENSE_LEVEL 0x02000000
171 #define TSI108_VECPRI_SENSE_EDGE 0x00000000
172 #define TSI108_VECPRI_POLARITY_MASK 0x01000000
173 #define TSI108_VECPRI_SENSE_MASK 0x02000000
174 #define TSI108_IRQ_DESTINATION 0x00004
178 MPIC_IDX_GREG_BASE = 0,
346 * Note setting any ID (leaving those bits to 0) means standard MPIC
353 #define MPIC_SECONDARY 0x00000001
356 #define MPIC_BIG_ENDIAN 0x00000002
358 #define MPIC_U3_HT_IRQS 0x00000004
360 #define MPIC_BROKEN_IPI 0x00000008
362 #define MPIC_SPV_EOI 0x00000020
364 #define MPIC_NO_PTHROU_DIS 0x00000040
366 #define MPIC_USES_DCR 0x00000080
368 #define MPIC_LARGE_VECTORS 0x00000100
370 #define MPIC_ENABLE_MCK 0x00000200
372 #define MPIC_NO_BIAS 0x00000400
374 #define MPIC_SINGLE_DEST_CPU 0x00001000
376 #define MPIC_ENABLE_COREINT 0x00002000
378 #define MPIC_NO_RESET 0x00004000
380 #define MPIC_FSL 0x00008000
385 #define MPIC_FSL_HAS_EIMR 0x00010000
388 #define MPIC_REGSET_MASK 0xf0000000
389 #define MPIC_REGSET(val) (((val) & 0xf ) << 28)
390 #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
392 #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
401 return 0; in fsl_mpic_primary_get_version()
411 * @isu_size: number of interrupts in an ISU. Use 0 to use a
414 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
425 * that is senses[0] correspond to linux irq "irq_offset".
468 /* Get the current cpu priority for this cpu (0..15) */