Lines Matching +full:0 +full:x00000
18 boot-bank = <0x0>;
34 #size-cells = <0>;
36 PowerPC,8548@0 {
38 reg = <0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
49 reg = <0x0 0x0>; // Filled in by boot loader
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
62 reg = <0x0 0x1000>;
68 reg = <0x1000 0x1000>;
75 reg = <0x2000 0x1000>;
82 reg = <0x20000 0x1000>;
84 cache-size = <0x80000>; // L2, 512K
92 #size-cells = <0>;
93 cell-index = <0>;
95 reg = <0x3000 0x100>;
102 * 0: BRD_CFG0 (1: P14 IO present)
113 reg = <0x18>;
116 polarity = <0x00>;
122 reg = <0x19>;
125 polarity = <0x00>;
130 reg = <0x50>;
136 reg = <0x68>;
141 reg = <0x34>;
148 #size-cells = <0>;
151 reg = <0x3100 0x100>;
161 reg = <0x21300 0x4>;
162 ranges = <0x0 0x21100 0x200>;
163 cell-index = <0>;
164 dma-channel@0 {
167 reg = <0x0 0x80>;
168 cell-index = <0>;
175 reg = <0x80 0x80>;
183 reg = <0x100 0x80>;
191 reg = <0x180 0x80>;
198 /* eTSEC1: Front panel port 0 */
202 cell-index = <0>;
206 reg = <0x24000 0x1000>;
207 ranges = <0x0 0x24000 0x1000>;
216 #size-cells = <0>;
218 reg = <0x520 0x20>;
223 reg = <0x1>;
228 reg = <0x2>;
233 reg = <0x3>;
238 reg = <0x4>;
241 reg = <0x11>;
255 reg = <0x25000 0x1000>;
256 ranges = <0x0 0x25000 0x1000>;
265 #size-cells = <0>;
267 reg = <0x520 0x20>;
270 reg = <0x11>;
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
294 #size-cells = <0>;
296 reg = <0x520 0x20>;
299 reg = <0x11>;
313 reg = <0x27000 0x1000>;
314 ranges = <0x0 0x27000 0x1000>;
323 #size-cells = <0>;
325 reg = <0x520 0x20>;
328 reg = <0x11>;
335 cell-index = <0>;
338 reg = <0x4500 0x100>;
339 clock-frequency = <0>;
349 reg = <0x4600 0x100>;
350 clock-frequency = <0>;
358 reg = <0xe0000 0x1000>;
364 #address-cells = <0>;
366 reg = <0x40000 0x40000>;
377 reg = <0xef005000 0x100>; // BRx, ORx, etc.
382 0 0x0 0xf8000000 0x08000000 // NOR boot flash
383 1 0x0 0xf0000000 0x08000000 // NOR expansion flash
384 2 0x0 0xe8000000 0x00010000 // NAND CE1
385 3 0x0 0xe8010000 0x00010000 // NAND CE2
388 nor-boot@0,0 {
392 reg = <0 0x0 0x4000000>;
395 partition@0 {
397 reg = <0x00000000 0x180000>;
401 reg = <0x00180000 0x180000>;
405 reg = <0x00300000 0x3c80000>;
409 reg = <0x03f80000 0x80000>;
413 nor-alternate@1,0 {
417 reg = <1 0x0 0x4000000>;
420 partition@0 {
422 reg = <0x00000000 0x3f80000>;
426 reg = <0x03f80000 0x80000>;
430 nand@2,0 {
434 reg = <2 0x0 0x10000>;
435 cle-line = <0x8>; /* CLE tied to A3 */
436 ale-line = <0x10>; /* ALE tied to A4 */
438 partition@0 {
440 reg = <0 0x40000000>;
452 reg = <0xef008000 0x1000>;
454 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
457 0xe000 0 0 1 &mpic 2 1
458 0xe000 0 0 2 &mpic 3 1>;
462 bus-range = <0 0>;
463 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
464 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
469 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
471 /* IDSEL 0x0 */
472 0x00000 0 0 1 &mpic 0 1
473 0x00000 0 0 2 &mpic 1 1
474 0x00000 0 0 3 &mpic 2 1
475 0x00000 0 0 4 &mpic 3 1>;
479 bus-range = <0 0xff>;
480 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
481 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
486 reg = <0xef00a000 0x1000>;
489 pcie@0 {
490 reg = <0 0 0 0 0>;
494 ranges = <0x02000000 0 0xc0000000 0x02000000 0
495 0xc0000000 0 0x20000000
496 0x01000000 0 0x00000000 0x01000000 0
497 0x00000000 0 0x08000000>;