Lines Matching +full:interrupt +full:- +full:partition +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 next-level-cache = <&L2>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
49 #address-cells = <1>;
50 #size-cells = <1>;
54 bus-frequency = <0>; // Filled in by U-Boot
55 compatible = "fsl,mpc8544-immr", "simple-bus";
57 ecm-law@0 {
58 compatible = "fsl,ecm-law";
60 fsl,num-laws = <10>;
64 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
67 interrupt-parent = <&mpic>;
70 memory-controller@2000 {
71 compatible = "fsl,mpc8544-memory-controller";
73 interrupt-parent = <&mpic>;
77 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8544-l2-cache-controller";
80 cache-line-size = <32>;
81 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
93 interrupt-parent = <&mpic>;
94 fsl,preserve-clocking;
104 interrupt-parent = <&mpic>;
113 interrupt-parent = <&mpic>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 cell-index = <1>;
122 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
125 interrupt-parent = <&mpic>;
126 fsl,preserve-clocking;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 cell-index = <0>;
138 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy0>;
142 tbi-handle = <&tbi0>;
143 phy-connection-type = "rgmii-id";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "fsl,gianfar-mdio";
151 phy0: ethernet-phy@0 {
152 interrupt-parent = <&mpic>;
156 phy1: ethernet-phy@1 {
157 interrupt-parent = <&mpic>;
161 tbi0: tbi-phy@11 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 cell-index = <1>;
176 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupt-parent = <&mpic>;
179 phy-handle = <&phy1>;
180 tbi-handle = <&tbi1>;
181 phy-connection-type = "rgmii-id";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,gianfar-tbi";
189 tbi1: tbi-phy@11 {
196 cell-index = <0>;
200 clock-frequency = <0>;
202 interrupt-parent = <&mpic>;
206 cell-index = <1>;
210 clock-frequency = <0>;
212 interrupt-parent = <&mpic>;
215 global-utilities@e0000 { //global utilities block
216 compatible = "fsl,mpc8548-guts";
218 fsl,has-rstcr;
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
226 compatible = "chrp,open-pic";
227 device_type = "open-pic";
233 compatible = "fsl,mpc8544-localbus",
234 "fsl,pq3-localbus",
235 "simple-bus";
236 #address-cells = <2>;
237 #size-cells = <1>;
239 interrupt-parent = <&mpic>;
245 >; /* Overwritten by U-Boot */
248 compatible = "amd,s29gl256n", "cfi-flash";
249 bank-width = <2>;
251 #address-cells = <1>;
252 #size-cells = <1>;
253 partition@0 {
256 read-only;
258 partition@1e0000 {
262 partition@200000 {
266 partition@400000 {
270 partition@3f80000 {
273 read-only;
275 partition@3fc0000 {
276 label = "u-boot";
278 read-only;
285 interrupt-parent = <&mpic>;
289 fpga_pic: fpga-pic@3,10 {
290 compatible = "abb,socrates-fpga-pic";
292 interrupt-controller;
293 /* IRQs 2, 10, 11, active low, level-sensitive */
295 interrupt-parent = <&mpic>;
296 #interrupt-cells = <3>;
300 compatible = "abb,socrates-spi";
303 interrupt-parent = <&fpga_pic>;
307 compatible = "abb,socrates-nand";
309 bank-width = <1>;
310 #address-cells = <1>;
311 #size-cells = <1>;
322 interrupt-parent = <&fpga_pic>;
327 #interrupt-cells = <1>;
328 #size-cells = <2>;
329 #address-cells = <3>;
330 compatible = "fsl,mpc8540-pci";
333 clock-frequency = <66666666>;
335 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
336 interrupt-map = <
341 interrupt-parent = <&mpic>;
343 bus-range = <0x0 0x0>;